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> DSDT

Differentiated System Description Table (DSDT) - DSDT is a part of the ACPI specification and it supplies configuration information about a base system. ACPI capable computers come with a preinstalled DSDT from the manufacturer. A common Linux/OS X problem is missing ACPI functionality (fans not running, laptop screens not shutting off, etc.)

This subforum is dedicated to patches/fixes able to be inserted/modified from an extracted dsdt.dsl, which is then compiled into a DSDT.aml for OS X to pick up and use (with a proper bootloader).

These fixes are not permanent, and do not damage your BIOS.

 
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> Fd—function Disable Register, How to use Function Disable Register
THe KiNG
post Dec 25 2009, 09:17 AM
Post #1
I will use in this example ICH7 IO Controller HUB specs and show you how to disable(enable) unused root ports as other...
To apply on other ICHx check the ICHx specs b/c some functions/registers may vary(e.g. ICH7 has only 4 UHCI ports and one EHCI).
The board used in this example is a mITX Intel ATOM board, that has only 1 PCI port.
You may use this guide on mATX or netbooks/notebooks.
I do not recommend using this stuff on full ATX boards, unless you know what you are doing...

So what is the benefit of this?
If you look on Apple ioregs(macmini/iMac or mobile) you will see almost on all root ports that are unused(they are not populated or dosen't get populated on card insertion) are disabled by default in EFI.
On our PC's are not, or worst on some crap BIOS some are not enabled(the right one..)
So what are the benefits other then cosmetic?
Each root port if is not disablet get IRQ's assigned, IRQ's are shared and in some cases conflicts may happen, not to mention that on our BIOS'es PCI IRQ routing table is pure crap on most cases, so to prevent an IRQ storm, here is how you can disable/enable them:

The registers part, see page 299, 7.1.56 FD—Function Disable Register, ICH7 IO Controller HUB:

CODE
OperationRegion (FDIS, SystemMemory, 0xFED1C000, 0x4000)
Field (FDIS, DWordAcc, Lock, Preserve)
{
Offset(0x3418), // Function Disable
, 1, // Offset: 3418h, Reserved
PATD, 1, // Offset: 3418h, Bit: 1 Parallel ATA Disable
SATD, 1, // Offset: 3418h, Bit: 2 Serial ATA Disable
SMBD, 1, // Offset: 3418h, Bit: 3 SM Bus Disable
HDAD, 1, // Offset: 3418h, Bit: 4 Intel High Definition Audio Disable
A97D, 1, // Offset: 3418h, Bit: 5 AC ‘97 Audio Disable
M97D, 1, // Offset: 3418h, Bit: 6 AC ‘97 Modem Disable
ILND, 1, // Offset: 3418h, Bit: 7 Internal LAN Disable
US1D, 1, // Offset: 3419h, UHCI #1 Disable
US2D, 1, // Offset: 3419h, Bit: 1 UHCI #2 Disable
US3D, 1, // Offset: 3419h, Bit: 2 UHCI #3 Disable
US4D, 1, // Offset: 3419h, Bit: 3 UHCI #4 Disable
, 2, // Offset: 3419h, Bit: 4&5 Reserved
LPBD, 1, // Offset: 3419h, Bit: 6 LPC Bridge Disable
EHCD, 1, // Offset: 3419h, Bit: 7 EHCI Disable
Offset(0x341A), // Function Disable Root Ports
RP1D, 1, // Offset: 341Ah, Root Port 1 Disable
RP2D, 1, // Offset: 341Ah, Bit: 1 Root Port 2 Disable
RP3D, 1, // Offset: 341Ah, Bit: 2 Root Port 3 Disable
RP4D, 1, // Offset: 341Ah, Bit: 3 Root Port 4 Disable
RP5D, 1, // Offset: 341Ah, Bit: 4 Root Port 5 Disable
RP6D, 1, // Offset: 341Ah, Bit: 5 Root Port 6 Disable
}


Now you can easy see what can be disabled/enabled, keep in mind that default value for enable is 0 and for disable is 1.
On my Atom board only first 2 root ports are used 0x001E0000(Also know in Apple DSDT as PCIB) for the PCI slot and 0x001C0000 for internal LAN, root port 3 and 4 are eating resources for nothing, 5 and 6 are disabled by Intel in EFI.

So lets disable RP03 and RP04:
Create a new Method right before _WAK one:

CODE
Method (PINI, 0, NotSerialized) // For PCI0/Wake INI
{
Store (One, RP3D)
Store (One, RP4D)
}


To make sure it will stay disabled after wake, we have to add a call for it on _WAK method:

CODE
Method (_WAK, 1, NotSerialized)
{
PINI ()
// ....... // Rest of your stuff from _WAK method
}


And finally call it on PCI0 _INI:

CODE
Device (PCI0)
{
Method (_INI, 0, NotSerialized)
{
PINI ()
}

// ....... //
}


That's it.

Enjoy!
tea
post Dec 25 2009, 11:14 AM
Post #2
Interesting, i'll try it on my desktop (ICH9R).
Thanks.
uncommah
post Dec 25 2009, 10:29 PM
Post #3
seems it works, but with some issues. for example if i disable UHCI #2, system doesn't boot and goes to reboot loop.

here's for ICH8
CODE
OperationRegion (FDIS, SystemMemory, 0xFED1C000, 0x4000) // IDE, LAN, USB, LPC, Intel HD Audio, SATA, or SMBus
Field (FDIS, DWordAcc, Lock, Preserve)
{
Offset (0x3418), // Function Disable
, 1, // bit 0 - BIOS must set this bit to 0b (0)
, 1, // bit 1 - Reserved
SA1D, 1, // bit 2 - Serial ATA Disable 1
SMBD, 1, // bit 3 - SM Bus Disable
HDAD, 1, // bit 4 - Intel High Definition Audio Disable
, 3, // bit 5-7 - Reserved
Offset (0x3419),
US1D, 1, // bit 8 - UHCI #1 Disable
US2D, 1, // bit 9 - UHCI #2 Disable
US3D, 1, // bit 10 - UHCI #3 Disable
US4D, 1, // bit 11 - UHCI #4 Disable (only with EHCI #2)
US5D, 1, // bit 12 - USB1 #5 Disable
EH2D, 1, // bit 13 - EHCI #2 Disable (only with UHCI #4)
LPBD, 1, // bit 14 - LPC Bridge Disable
EH1D, 1, // bit 15 - EHCI #1 Disable
Offset (0x341A), // Function Disable Root Ports
RP1D, 1, // bit 16 - PCI Express 1 Disable
RP2D, 1, // bit 17 - PCI Express 2 Disable
RP3D, 1, // bit 18 - PCI Express 3 Disable
RP4D, 1, // bit 19 - PCI Express 4 Disable
RP5D, 1, // bit 20 - PCI Express 5 Disable
RP6D, 1, // bit 21 - PCI Express 6 Disable
, 2, // bit 22-23 - Reserved
Offset (0x341B),
THTD, 1, // bit 24 - Thermal Throttle Disable
SA2D, 1, // bit 25 - Serial ATA Disable 2
Offset (0x3420), // Function Disable SUS Well
LNDS, 1 // LAN Disable
}
Asus V1Sn ~ MacBookPro4,1
Intel® Core 2 Duo T9300 (2.5GHz) / DDR2 667 MHz / NVIDIA GeForce 9500M GS 512MB / Mobile Intel® PM965 Express + ICH8 / ALC660 / Intel® Wireless WiFi Link 4965AGN Apple Atheros AR5008 / eSATA (JMicron JMB360) / Intel® 82566MM Gigabit Ethernet
THe KiNG
post Dec 26 2009, 12:02 AM
Post #4
QUOTE (uncommah @ Dec 25 2009, 11:29 PM) *
seems it works, but with some issues. for example if i disable UHCI #2, system doesn't boot and goes to reboot loop.


There is a reason why I posted the page of the specs...:

QUOTE
The UHCI functions must be disabled from highest function number to lowest. For
example, if only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set).
When disabling UHCIs, the EHCI Structural Parameters Registers must be updated with
coherent information in “Number of Companion Controllers” and “N_Ports” fields.


Read first, disable after.
18seven
post Jan 3 2010, 02:40 AM
Post #5
I can't seem to write to anything on IHC7-M/945GME, I have tried the cosmetic sub dev id injections, + some, on the other post as well. Is a global lock possible? I have been searching and cannot find a reason.
THe KiNG
post Jan 6 2010, 03:37 PM
Post #6
So far worked on all my hardware, ICH7, ICH8-M and ICH10R.
Check the registers again with specs in hand.
barnum
post Mar 15 2010, 10:06 AM
Post #7
QUOTE (THe KiNG @ Jan 6 2010, 04:37 PM) *
So far worked on all my hardware, ICH7, ICH8-M and ICH10R.
Check the registers again with specs in hand.


Hi the King,

I have an ASUS P5Q PRO with ICH10R,
Can you tell me what did you disable on your ICH10R motherboard ?

Regards,
Barnum

Maverick 10.9.5 retail
yosemite 10.10 beta 3 retail

Motherboard: Asus P6TWS PRO
oldnapalm
post May 2 2010, 01:42 AM
Post #8
Hello there,

I'm trying to use this on ICH9 http://www.intel.com/design/chipsets/datashts/316972.htm

Here's what I have done so far
CODE
OperationRegion (FDIS, SystemMemory, 0xFED1C000, 0x4000)
Field (FDIS, DWordAcc, Lock, Preserve)
{
Offset(0x3418), // Function Disable
, 1, // Offset: 3418h, Bit: 0 BIOS must set this bit to 1b
, 1, // Offset: 3418h, Bit: 1 Reserved
SAD1, 1, // Offset: 3418h, Bit: 2 Serial ATA Disable 1
SD, 1, // Offset: 3418h, Bit: 3 SM Bus Disable
HDAD, 1, // Offset: 3418h, Bit: 4 Intel High Definition Audio Disable
, 2, // Offset: 3418h, Bit: 5:6 Reserved
U6D, 1, // Offset: 3418h, Bit: 7 UHCI #6 Disable
U1D, 1, // Offset: 3419h, Bit: 8 UHCI #1 Disable
U2D, 1, // Offset: 3419h, Bit: 9 UHCI #2 Disable
U3D, 1, // Offset: 3419h, Bit: 10 UHCI #3 Disable
U4D, 1, // Offset: 3419h, Bit: 11 UHCI #4 Disable
U5D, 1, // Offset: 3419h, Bit: 12 UHCI #5 Disable
E2D, 1, // Offset: 3419h, Bit: 13 EHCI #2 Disable
LBD, 1, // Offset: 3419h, Bit: 14 LPC Bridge Disable
E1D, 1, // Offset: 3419h, Bit: 15 EHCI #1 Disable
Offset(0x341A), // Function Disable Root Ports
PE1D, 1, // Offset: 341Ah, Bit: 16 PCI Express 1 Disable
PE2D, 1, // Offset: 341Ah, Bit: 17 PCI Express 2 Disable
PE3D, 1, // Offset: 341Ah, Bit: 18 PCI Express 3 Disable
PE4D, 1, // Offset: 341Ah, Bit: 19 PCI Express 4 Disable
PE5D, 1, // Offset: 341Ah, Bit: 20 PCI Express 5 Disable
PE6D, 1, // Offset: 341Ah, Bit: 21 PCI Express 6 Disable
Offset(0x341B),
TTD, 1, // Offset: 341Bh, Bit: 24 Thermal Throttle Disable
SAD2, 1, // Offset: 341Bh, Bit: 25 Serial ATA Disable 2
}


One thing that I didn't understand: where do the vaules 0xFED1C000 and 0x4000 come from?

Thank you.
hotcorez
post Aug 17 2010, 09:44 PM
Post #9
Thanks for this great info King. To see how this table looks in another dsdt, have a look at the mbp3,1 dsdt. I will be having a look at it to learns how to properly implement this!

Choose a mac with a matching chipset and you can see the correct code in the correspoding dsdt.

I am starting to realize all these hacks are just putting stuff in that mac dsdt already has!!

Cheers,

LS
XPbIM3
post Sep 20 2010, 07:30 PM
Post #10
QUOTE (oldnapalm @ May 2 2010, 07:42 AM) *
where do the vaules 0xFED1C000 ..... come from?

Same question. 0xFED1C000 - must be a most-used value. But we must be careful, in some cases it may be different.
Am i right?


CODE
                OperationRegion (C099, SystemMemory, 0xFED90000, 0x4000)
                Field (C099, DWordAcc, NoLock, Preserve)
                {
                            Offset (0x3404),
                    C09A,   2,
                        ,   5,
                    C09B,   1,
                            Offset (0x3418),
                    C09C,   32
                }


This post has been edited by XPbIM3: Sep 20 2010, 07:34 PM
P6TSE, i7 920 @4.2Ghz, GTS250, 10.6.4 x64
HP TC4400, C2D T7200 running on both cores ;)
THe KiNG
post Sep 20 2010, 08:18 PM
Post #11
I though I was very clear in the first post, if not: READ YOUR BOARD CHIPSET DATASHEET!
Here example from ICH8 one:




In translation:
OperationRegion (FDIS, SystemMemory, RCBA, OffsetLenght)

Do NOT copy/paste code from other DSDT's/examples until you double check if it match your chipset and memory registers!

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