ProjectOSX

Welcome Guest!

Returning User? Login here.

Want membership privileges? Register here.

> DSDT

Differentiated System Description Table (DSDT) - DSDT is a part of the ACPI specification and it supplies configuration information about a base system. ACPI capable computers come with a preinstalled DSDT from the manufacturer. A common Linux/OS X problem is missing ACPI functionality (fans not running, laptop screens not shutting off, etc.)

This subforum is dedicated to patches/fixes able to be inserted/modified from an extracted dsdt.dsl, which is then compiled into a DSDT.aml for OS X to pick up and use (with a proper bootloader).

These fixes are not permanent, and do not damage your BIOS.

2 Pages V   1 2 >  
Start a new topic Add Reply
> Ioatafamily Panic Fix, How to fix the panic and get rid of ugly boot warning...
THe KiNG
post Nov 2 2009, 01:44 PM
Post #1
Hi,

Thanks to Galaxy who provided full dumps from his MacBookPro, ApexDE who founded the fix for J-Micron AHCI(and made me curious how he did it) and to Kabyl that always point me to the right docs, I was able to fix that IOATAFamily panic and that ugly "AppleIntelPIIXPATA: Secondary PCI IDE channel is disabled" warning on boot with a DSDT fix.

Find your Intel PATA controller in DSDT, should be on 0x001F0001, and add this code:
CODE
OperationRegion (IDET, PCI_Config, 0x40, 0x04) // IDE Timing Register
Field (IDET, WordAcc, NoLock, Preserve)
{
Offset (0x00),
M1, 8,
Offset (0x01),
M2, 8,
Offset (0x02),
M3, 8,
Offset (0x03),
M4, 8
}

Method (_DSM, 4, NotSerialized)
{
Store (0x07, M1)
Store (0xE3, M2)
Store (Zero, M3)
Store (0xC0, M4)
Return (Zero)
}


Enjoy using original kext and a clean verbose boot tongue.gif

L.E. This fix is only for Intel PATA controller!
Clubber_77
post Nov 2 2009, 06:01 PM
Post #2
Works! Thanks! wink.gif
MacKleriker
post Nov 2 2009, 07:34 PM
Post #3
Yep, works fine!

Thank you...

cYa
Slice
post Nov 2 2009, 08:44 PM
Post #4
Thank you! It works.
This patch eliminates necessory in my driver
http://www.projectosx.com/forum/index.php?...ic=676&st=0
Пожалуйста, прочитайте ЧаВо!
i3-2120 GA-H61M-S1, Radeon HD6670, ALC887(VoodooHDA 2.8.4), OS⌘10.9.2, OS⌘ 10.7.5 Clover FakeSMC_plugins_3.3.1 Realtek LAN v3.1.2
THe KiNG
post Nov 2 2009, 09:07 PM
Post #5
Glad that I see other peopple happy with this fix(it dosen't actually enable the secondary port, you can see that Region 0 & 1 I/O ports are <unassigned>, but is a easy way to trick the driver)
Innerz
post Nov 4 2009, 01:39 PM
Post #6
First of all, thank you so much THe KiNG for finding this DSDT trick smile.gif

I have a 965P-DS4 (ICH-8R). I don't know where to paste the provided code by THe KiNG.

CODE
Device (IDE1)
{
Name (_ADR, 0x001F0002)
OperationRegion (PCI, PCI_Config, 0x40, 0x20)
Field (PCI, DWordAcc, NoLock, Preserve)
{
ITM0, 16,
ITM1, 16,
SIT0, 4,
SIT1, 4,
Offset (0x08),
UDC0, 2,
UDC1, 2,
Offset (0x0A),
UDT0, 8,
UDT1, 8,
Offset (0x14),
ICF0, 2,
ICF1, 2,
, 6,
WPPE, 1,
, 1,
FAS0, 2,
FAS1, 2
}

Device (PRIM)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
Store (GTM (ITM0, SIT0, UDC0, UDT0, ICF0, FAS0), Local0)
Return (Local0)
}

Method (_STM, 3, NotSerialized)
{
Store (STM (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, Zero, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
CreateDWordField (Local0, 0x14, FAS)
Store (UDC, UDC0)
Store (UDT, UDT0)
Store (ICF, ICF0)
Store (FAS, FAS0)
}

Device (DRV0)
{
Name (_ADR, Zero)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF0 (ITM0, SIT0, UDC0, UDT0, ICF0, H15F, FAS0), Local0)
Return (Local0)
}
}

Device (DRV1)
{
Name (_ADR, One)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF1 (ITM0, SIT0, UDC0, UDT0, ICF0, H15F, FAS0), Local0)
Return (Local0)
}
}
}

Device (SECD)
{
Name (_ADR, One)
Method (_GTM, 0, NotSerialized)
{
Store (GTM (ITM1, SIT1, UDC1, UDT1, ICF1, FAS1), Local0)
Return (Local0)
}

Method (_STM, 3, NotSerialized)
{
Store (STM (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, Zero, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
CreateDWordField (Local0, 0x14, FAS)
Store (UDC, UDC1)
Store (UDT, UDT1)
Store (ICF, ICF1)
Store (FAS, FAS1)
}

Device (DRV0)
{
Name (_ADR, Zero)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF0 (ITM1, SIT1, UDC1, UDT1, ICF1, H15F, FAS1), Local0)
Return (Local0)
}
}

Device (DRV1)
{
Name (_ADR, One)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF1 (ITM1, SIT1, UDC1, UDT1, ICF1, H15F, FAS1), Local0)
Return (Local0)
}
}
}
}


I'll be thankful if someone can help me.

This post has been edited by Innerz: Nov 5 2009, 12:11 PM
Jingu
post Nov 4 2009, 09:58 PM
Post #7
Okay, I manage to find the section and I added the code right after the first "}" under Device (PATA)

CODE
Device (PATA)
{
Name (_ADR, 0x001F0001)
OperationRegion (PACS, PCI_Config, 0x40, 0xC0)
Field (PACS, DWordAcc, NoLock, Preserve)
{
PRIT, 16,
Offset (0x04),
PSIT, 4,
Offset (0x08),
SYNC, 4,
Offset (0x0A),
SDT0, 2,
, 2,
SDT1, 2,
Offset (0x14),
ICR0, 4,
ICR1, 4,
ICR2, 4,
ICR3, 4,
ICR4, 4,
ICR5, 4
}

OperationRegion (IDET, PCI_Config, 0x40, 0x04)
Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 8,
M2, 8,
M3, 8,
M4, 8
}

Method (_DSM, 4, NotSerialized)
{
Store (0x07, M1)
Store (0xE3, M2)
Store (Zero, M3)
Store (0xC0, M4)
Return (Zero)
}


But after compiling dsdt.dsl into dsdt.aml

Field (IDET, WordAcc, NoLock, Preserve)
{
Offset (0x00),
M1, 8,
Offset (0x01),
M2, 8,
Offset (0x02),
M3, 8,
Offset (0x03),
M4, 8
}

keeps becoming:

Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 8,
M2, 8,
M3, 8,
M4, 8
}

BUT IT STILL WORKS! THANKS. And I don't see anymore the secondary PCI IDE channel disabled warning.

When booting up, there is however about a 10 second pause on the line: FireWire runtime power conservation disabled. (2)

This post has been edited by Jingu: Nov 4 2009, 10:05 PM
THe KiNG
post Nov 5 2009, 05:14 AM
Post #8
Was hard to find out?
I guess not tongue.gif
The offset is there that you will easy know what/where you change stuff...
Do lspci -nnvvxxx then look under IDE1(PATA) @ 40: m1 m2 m3 m4.... and you will understand.
Jingu
post Nov 5 2009, 11:27 AM
Post #9
Yes, that was very easy to find.

I used the search function to look for occurrences of the 0x001F0001 address that you mentioned. It took me straight to the Device (PATA) section!

I understand that the offset is still there. It works fine in both 32 bit and 64 bit and that's all that matters.

This post has been edited by Jingu: Nov 5 2009, 11:32 AM
Innerz
post Nov 5 2009, 12:05 PM
Post #10
The problem is, i don't have the "0x001F0001" offset.

lspci -nnvvxxx give me this result :

CODE
04:00.0 IDE interface [0101]: JMicron Technology Corp. JMB362/JMB363 AHCI Controller [197b:2363] (rev 02) (prog-if 85 [Master SecO PriO])
Subsystem: Giga-byte Technology GA-EP45-DS5 Motherboard [1458:b000]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 17
Region 0: I/O ports at a000
Region 1: I/O ports at a400
Region 2: I/O ports at a800
Region 3: I/O ports at ac00
Region 4: I/O ports at b000
Region 5: Memory at ee100000 (32-bit, non-prefetchable)
Capabilities: [68] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] Express (v1) Legacy Endpoint, MSI 01
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Suprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100] #197b
Capabilities: [236] #68
00: 7b 19 63 23 07 00 10 00 02 85 01 01 08 00 00 00
10: 01 a0 00 00 01 a4 00 00 01 a8 00 00 01 ac 00 00
20: 01 b0 00 00 00 00 10 ee 00 00 00 00 58 14 00 b0
30: 00 00 00 00 68 00 00 00 00 00 00 00 11 01 00 00
40: b1 51 c0 00 cc 08 ff e0 20 00 00 24 00 00 00 00
50: 10 00 11 02 00 00 00 00 00 20 00 00 11 f4 03 01
60: 00 00 11 10 00 00 00 00 01 50 02 40 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 08 a0 00 a0 01 0a 00 0f aa 0f 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: c3 8b 38 00 03 45 02 00 9c 34 27 c0 49 92 00 00
d0: 18 00 80 80 01 00 00 00 00 00 eb 00 00 00 00 01
e0: 00 00 00 00 00 00 00 00 9c 34 27 c0 49 92 00 89
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Here my Attached File  DSDT.dsl.zip ( 13.18K ) Number of downloads: 46


This post has been edited by Innerz: Nov 5 2009, 12:11 PM
THe KiNG
post Nov 5 2009, 04:34 PM
Post #11
What are you trying to do?
Do you have panic on IOATAFamily?
From what I see you have J-Micron IDE controller, do you want it as AHCI or what?
Innerz
post Nov 5 2009, 04:44 PM
Post #12
I've an IDE DVD Drive, and JMicronATA.kext or IOATAFamily give me a kernel panic. I just want to be able to use my IDE drive. In AHCI, the IDE port seems not working at all.

This post has been edited by Innerz: Nov 5 2009, 04:45 PM
THe KiNG
post Nov 5 2009, 05:20 PM
Post #13
Sorry mate, this fix is only for Intel PATA controller, if J-MicronATA.kext dosen't work for you then you are out of luck or you need a better jmicron driver.
Innerz
post Nov 5 2009, 05:30 PM
Post #14
Anyway, thank you for your work smile.gif
jadran
post Nov 6 2009, 11:35 AM
Post #15
thx, tested on asrock with atom 330, works!
THe KiNG
post Nov 6 2009, 02:56 PM
Post #16
OK seems I have to explain again for some why I did it this way.
The purpose of the comments(including the offsets) was for other to easy understand what does this modifications and why/where is the fix.
I know I can use 16 bit registers(I'm not blind and can read myself in specs) but that way people will not understand what is the fix, and apply it blindly...
Indeed INI Method is better if you don't inject other stuff in same space...

But what a hell?
For those who are so "elevate" here is the new fix:
CODE
OperationRegion (IDET, PCI_Config, 0x40, 0x04)
Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 16,
M2, 16
}

Method (_INI, 0, NotSerialized)
{
Store (0xE307, M1)
Store (0xC000, M2)
}

To preserve the settings after sleep/wake add this on _WAK method:
CODE
Method (_WAK, 1, NotSerialized)
{
\_SB.PCI0.PATA._INI ()

..............................
Return (Package (0x02)
{
Zero,
Zero
})
}


@MasterChief if you have enough "balls" came here and comment my work, don't act like a chicken and comment my stuff on a forum where you know I can't reply, don't be afraid I will not ban you.
uncommah
post Nov 6 2009, 08:02 PM
Post #17
THe KiNG,
how did you get the exact data of those registers?
Asus V1Sn ~ MacBookPro4,1
Intel® Core 2 Duo T9300 (2.5GHz) / DDR2 667 MHz / NVIDIA GeForce 9500M GS 512MB / Mobile Intel® PM965 Express + ICH8 / ALC660 / Intel® Wireless WiFi Link 4965AGN Apple Atheros AR5008 / eSATA (JMicron JMB360) / Intel® 82566MM Gigabit Ethernet
THe KiNG
post Nov 6 2009, 08:30 PM
Post #18
QUOTE (uncommah @ Nov 6 2009, 09:02 PM) *
THe KiNG,
how did you get the exact data of those registers?

Intel® ICH8 Family Datasheet page 547:
QUOTE
13.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
Note: This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.

And I said in first post, Galaxy provided me full dumps from his MacBookPro(ICH8-M)
jadran
post Nov 7 2009, 09:17 AM
Post #19
QUOTE (THe KiNG @ Nov 6 2009, 03:56 PM) *
To preserve the settings after sleep/wake add this on _WAK method:
CODE
Method (_WAK, 1, NotSerialized)
{
\_SB.PCI0.PATA._INI ()

..............................
Return (Package (0x02)
{
Zero,
Zero
})
}


This should ba added for any board no mater what. What U think King?
I saw this in any mac dsdt.
THe KiNG
post Nov 7 2009, 11:18 AM
Post #20
QUOTE (jadran @ Nov 7 2009, 10:17 AM) *
This should ba added for any board no mater what. What U think King?
I saw this in any mac dsdt.

I wa refering on this line:
\_SB.PCI0.PATA._INI ()

2 Pages V   1 2 >
Add Reply Start a new topic
1 User(s) are reading this topic (1 Guests and 0 Anonymous Users)
0 Members: