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> DSDT

Differentiated System Description Table (DSDT) - DSDT is a part of the ACPI specification and it supplies configuration information about a base system. ACPI capable computers come with a preinstalled DSDT from the manufacturer. A common Linux/OS X problem is missing ACPI functionality (fans not running, laptop screens not shutting off, etc.)

This subforum is dedicated to patches/fixes able to be inserted/modified from an extracted dsdt.dsl, which is then compiled into a DSDT.aml for OS X to pick up and use (with a proper bootloader).

These fixes are not permanent, and do not damage your BIOS.

 
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> Smbus(sbus), How to fix AppleSMBusPCI error
THe KiNG
post Nov 3 2009, 09:30 PM
Post #1
Users with X58 boards may get the AppleSMBusPCI error on boot b/c the SMBus device-id match with apple one, and OS X expect to find DLV0 device..
Some n00b think that if you copy/paste apple data from original MacPro DSDT actually make it working, and the "prove" was that AppleSMBusPCI.kext is loaded.

Well what if we get the very same result with just this code?
CODE
Device (SBUS)
{
Name (_ADR, 0x001F0003)
Device (BUS0)
{
Name (_CID, "smbus")
Name (_ADR, Zero)
Device (DVL0)
{
Name (_ADR, 0x57)
Name (_CID, "diagsvault")
}
}
}

No more errors and the kext is loaded...

Full SMBus implementation require more then just one neuron..and I'm not sure if is even possible, but well we can put our brain on work and try.
Our best luck may be on mobile platforms since on notebooks we do have Embedded Controller(EC).
I think we need first to understand how/what does apple code, so I started to dig deep and find what does those registers and methods in our region of interest:

CODE

// Global ACPI memory region(GNVS/BIOS on PC) This region is used for
// passing information between system BIOS, ACPI, and the SMI handler.

OperationRegion (GNVS, SystemMemory, 0x7F556D98, 0x0100)
Field (GNVS, AnyAcc, Lock, Preserve)
{
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter
PRM1, 8, // 0x04 - SMI function parameter
SCIF, 8, // 0x05 - SCI function
PRM2, 8, // 0x06 - SCI function parameter
PRM3, 8, // 0x07 - SCI function parameter
LCKF, 8, // 0x08 - Global Lock function for EC
PRM4, 8, // 0x09 - Lock function parameter
PRM5, 8, // 0X0A - Lock function parameter
P80D, 32, // 0X0B - Debug port (IO 0x80) value
LIDS, 8, // 0X0F - LID state (Open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS
Offset (0x14), // Thermal policy
ACTT, 8, // 0x14 - Active trip point
PSVT, 8, // 0x15 - Passive trip point
TC1V, 8, // 0x16 - Passive trip point TC1
TC2V, 8, // 0x17 - Passive trip point TC2
TSPV, 8, // 0x18 - Passive trip point TSP
CRTT, 8, // 0x19 - Critical trip point
DTSE, 8, // 0X1A - Digital Thermal Sensor Enable
DTS1, 8, // 0X1B - Digital Thermal Sensor 1
DTS2, 8, // 0X1C - Digital Thermal Sensor 2
DTSF, 8, // 0X1D - Digital Thermal Sensor Function ??
// Battery Support
BNUM, 8, // 0X1E - Number of batteries
B0SC, 8, // 0X1F - BAT0 stored capacity
B1SC, 8, // 0x20 - BAT1 stored capacity
B2SC, 8, // 0x21 - BAT2 stored capacity
B0SS, 8, // 0x22 - BAT0 stored status
B1SS, 8, // 0x23 - BAT1 stored status
B2SS, 8, // 0x24 - BAT2 stored status
Offset (0x28), // Processor Identification
APIC, 8, // 0x28 - APIC Enabled
MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0X2A - PDC CPU/CORE 0
PCP1, 8, // 0X2B - PDC CPU/CORE 1
PPCM, 8, // 0X2C - Max. PPC state
PPMF, 32, // 0x31 - ??
Offset (0x32), // Super I/O & CMOS configuration
NATP, 8, // 0x32 - ??
CMAP, 8, // 0x33 - ??
CMBP, 8, // 0x34 - ??
LPTP, 8, // 0x35 - LPT port
FDCP, 8, // 0x36 - FDC port
CMCP, 8, // 0x37 - COM port
CIRP, 8, // 0x38 - CIR port
Offset (0x3C), // Integrated Graphics Device
IGDS, 8, // 0X3C - IGD state (primary = 1)
TLST, 8, // 0X3D - Display Toggle List pointer
CADL, 8, // 0X3E - Currently Attached Devices List
PADL, 8, // 0X3F - Previously Attached Devices List
CSTE, 16, // 0x40 - Current display state
NSTE, 16, // 0x42 - Next display state
SSTE, 16, // 0x44 - Set display state
NDID, 8, // 0x46 - Number of Device IDs
DID1, 32, // 0x47 - Device ID 1
DID2, 32, // 0X4B - Device ID 2
DID3, 32, // 0X4F - Device ID 3
DID4, 32, // 0x53 - Device ID 4
DID5, 32, // 0x57 - Device ID 5
BDSP, 8, // 0X5B - ??
PTY1, 8, // 0X5C - ??
PTY2, 8, // 0X5D - ??
PSCL, 8, // 0X5E - ??
TVF1, 8, // 0X5F - ??
TVF2, 8, // 0x60 - ??
Offset (0x63),
GOPB, 32, // 0x63 - ??
BLCS, 8, // 0x67 - Backlight control status/supported ?
BRTL, 8, // 0x68 - Brightness Level
ALSE, 8, // 0x69 - Ambient Light Sensor Enable
ALAF, 8, // 0X6A - Ambient Light Adjustment Factor
LLOW, 8, // 0x6B - LUX Low
LHIH, 8, // 0x6C - LUX High
Offset (0x6E), // EMA
EMAE, 8, // 0X6E - EMA Enable
EMAP, 16, // 0x70 - EMA Pointer
EMAL, 16, // 0x72 - EMA Length
Offset (0x74), // MEF
MEFE, 8, // 0x74 - MEF Enable
Offset (0x82), // SATA
GTF0, 56, // 0x82 - GTF task file buffer for port 0
GTF2, 56, // 0x87 - GTF task file buffer for port 2
IDEM, 8, // 0X9A - IDE mode (compatible / enhanced)
GTF1, 56 // 0x96 - GTF task file buffer for port 1
}


CODE
Device (EC) // Embedded Controller
{
Name (_HID, EisaId ("PNP0C09"))
Name (_CRS, ResourceTemplate () // Current Resource Settings
{
IO (Decode16,
0x0062, // Range Minimum
0x0062, // Range Maximum
0x00, // Alignment
0x01, // Length
)
IO (Decode16,
0x0066, // Range Minimum
0x0066, // Range Maximum
0x00, // Alignment
0x01, // Length
)
})
Name (_GPE, 0x17) // GPE index for this EC, GPI07 / GPE23 -> Runtime SCI
Name (_PRW, Package (0x02) // Power Resources for Wake
{
0x1B,
0x03
})
Name (ECOK, Zero)
OperationRegion (ECOR, EmbeddedControl, Zero, 0xFF)
Field (ECOR, ByteAcc, Lock, Preserve)
{
ECVS, 8, // EC Version
LSTE, 1, // LID Controll
RPWR, 1, // Power Controll
CDIN, 1, // CD Controll
Offset (0x02),
LWAK, 1, // LID Wake
ACWK, 1, // AC Wake
CDWK, 1, // CD Wake
Offset (0x03),
G3HT, 1, // ??
Offset (0x04),
Offset (0x10),
ECSS, 8, // EC Status
PLIM, 8, // ??
Offset (0x20),
SPTR, 8, // SMBus Protocol
SSTS, 8, // SMBus Status
SADR, 8, // SMBus Address
SCMD, 8, // SMBus Command
SBFR, 256, // SMBus Buffer
SCNT, 8, // SMBus Control
SAAD, 8, // SMBus Alarm Address
SAD0, 8, // SMBus Alarm Data Byte 0
SAD1, 8, // SMBus Alarm Data Byte 1
SMUX, 8 // SMBus multi level i2c MUX(multiplexing)
}

Method (_Q5A, 0, NotSerialized) // Embedded controller event
{
Notify (PWRB, 0x80) // Power Button Notifier
}

Method (_Q80, 0, NotSerialized) // Embedded controller event
{
PNOT () // Power Management Notifier
}
// This method is needed by Windows XP/2000 for EC initialization before a driver is loaded
Method (_REG, 2, NotSerialized)
{
If (LOr (LEqual (Arg0, 0x03), LGreaterEqual (OSYS, 0x07D6)))
{
Store (Arg1, ECOK)
If (LEqual (Arg1, One))
{
Store (Zero, ECSS)
}
}
}
}


CODE
Device (SBUS) // Intel SMBus Controller
{
Name (_ADR, 0x001F0003)
OperationRegion (SMBP, PCI_Config, 0x40, 0xC0)
Field (SMBP, DWordAcc, NoLock, Preserve)
{
, 2,
I2CE, 1
}

OperationRegion (SMBE, PCI_Config, 0x04, 0x02)
Field (SMBE, AnyAcc, NoLock, Preserve)
{
IOSE, 1 // I/O Space Enable
}

OperationRegion (SMBI, SystemIO, 0x4000, 0x10)
Field (SMBI, ByteAcc, NoLock, Preserve)
{
HSTS, 8, // Host Status
Offset (0x02),
HCON, 8, // Host Control
HCOM, 8, // Host Command
TXSA, 8, // Transmit Slave Address
DAT0, 8, // Host Data Byte 0
DAT1, 8, // Host Data Byte 1
HBDR, 8, // Host Block Data
PECR, 8, // Packet Error Check
RXSA, 8, // Receive Slave Address
SDAT, 16 // Receive Slave Data
}

Name (SBOK, Zero)
Method (ENAB, 0, NotSerialized) // Enable Method
{
Store (One, IOSE)
Store (One, SBOK)
}

Method (DISB, 0, NotSerialized) // Disable Method
{
Store (Zero, SBOK)
}

Method (SSXB, 2, Serialized) // SMBus Send Byte(Arg0:Address, Arg1:Data)
{
If (STRT ()) // Is the SMBus Controller Ready?
{
Return (Zero) // Failure
}

// Send Byte
Store (Zero, I2CE) // SMBus Enable
Store (0xBF, HSTS)
Store (Arg0, TXSA) // Write Address
Store (Arg1, HCOM) // Write Data
Store (0x48, HCON) // Start + Byte Data Protocol
If (COMP ()) // Check if last operation completed
{
Or (HSTS, 0xFF, HSTS) // Clean up
Return (One) // Success
}

Return (Zero) // Failure
}
// SMBus Receive Byte(Arg0:Address, Return:0xffff=Failure, Data (8bit)=Success)
Method (SRXB, 1, Serialized)
{
If (STRT ()) // Is the SMBus Controller Ready?
{
Return (0xFFFF)
}

// Receive Byte
Store (Zero, I2CE) // SMBus Enable
Store (0xBF, HSTS)
Store (Or (Arg0, One), TXSA) // Write Address
Store (0x44, HCON) // Start
If (COMP ()) // Check if last operation completed
{
Or (HSTS, 0xFF, HSTS) // Clean up
Return (DAT0) // Success
}

Return (0xFFFF)
}

Method (SWRB, 3, Serialized) // SMBus Write Byte
{
If (STRT ()) // Is the SMBus Controller Ready?
{
Return (Zero) // Failure
}

Store (Zero, I2CE) // SMBus Enable
Store (0xBF, HSTS)
Store (Arg0, TXSA) // Write Address
Store (Arg1, HCOM) // Write Command
Store (Arg2, DAT0) // Write Data
Store (0x48, HCON) // Start + Byte Protocol
If (COMP ()) // Check if last operation completed
{
Or (HSTS, 0xFF, HSTS) // Clean up
Return (One) // Success
}

Return (Zero) // Failure
}

Method (SRDB, 2, Serialized) // SMBus Read Byte(Arg0:Address,Arg1:Command, Return:0xffff=Failure, Data (8bit)=Success)
{
If (STRT ()) // Is the SMBus Controller Ready?
{
Return (0xFFFF)
}

Store (Zero, I2CE) // SMBus Enable
Store (0xBF, HSTS)
Store (Or (Arg0, One), TXSA) // Write Address
Store (Arg1, HCOM) // Write Command
Store (0x48, HCON) // Start + Byte Protocol
If (COMP ()) // Check if last operation completed
{
Or (HSTS, 0xFF, HSTS) // Clean up
Return (DAT0) // Success
}

Return (0xFFFF)
}

Method (SBLW, 4, Serialized) // Single Bit Line Write?
{
If (STRT ()) // Is the SMBus Controller Ready?
{
Return (Zero) // Failure
}

Store (Arg3, I2CE)
Store (0xBF, HSTS)
Store (Arg0, TXSA)
Store (Arg1, HCOM) // Write Command
Store (SizeOf (Arg2), DAT0)
Store (Zero, Local1)
Store (DerefOf (Index (Arg2, Zero)), HBDR)
Store (0x54, HCON)
While (LGreater (SizeOf (Arg2), Local1))
{
Store (0x0FA0, Local0)
While (LAnd (LNot (And (HSTS, 0x80)), Local0))
{
Decrement (Local0)
Stall (0x32)
}

If (LNot (Local0))
{
KILL ()
Return (Zero)
}

Store (0x80, HSTS)
Increment (Local1)
If (LGreater (SizeOf (Arg2), Local1))
{
Store (DerefOf (Index (Arg2, Local1)), HBDR)
}
}

If (COMP ()) // Check if last operation completed
{
Or (HSTS, 0xFF, HSTS) // Clean up
Return (One) // Success
}

Return (Zero) // Failure
}

Method (SBLR, 3, Serialized) // Single Bit Line Read?
{
Name (TBUF, Buffer (0x0100) {})
If (STRT ())
{
Return (Zero)
}

Store (Arg2, I2CE)
Store (0xBF, HSTS)
Store (Or (Arg0, One), TXSA)
Store (Arg1, HCOM)
Store (0x54, HCON)
Store (0x0FA0, Local0)
While (LAnd (LNot (And (HSTS, 0x80)), Local0))
{
Decrement (Local0)
Stall (0x32)
}

If (LNot (Local0))
{
KILL ()
Return (Zero)
}

Store (DAT0, Index (TBUF, Zero))
Store (0x80, HSTS)
Store (One, Local1)
While (LLess (Local1, DerefOf (Index (TBUF, Zero))))
{
Store (0x0FA0, Local0)
While (LAnd (LNot (And (HSTS, 0x80)), Local0))
{
Decrement (Local0)
Stall (0x32)
}

If (LNot (Local0))
{
KILL ()
Return (Zero)
}

Store (HBDR, Index (TBUF, Local1))
Store (0x80, HSTS)
Increment (Local1)
}

If (COMP ())
{
Or (HSTS, 0xFF, HSTS)
Return (TBUF)
}

Return (Zero)
}

Method (STRT, 0, Serialized) // Wait for SMBus to become ready
{
Store (0xC8, Local0) // Timeout 200ms
While (Local0)
{
If (And (HSTS, 0x40)) // IN_USE?
{
Decrement (Local0)
Sleep (One) // Wait 1ms
If (LEqual (Local0, Zero)) // timeout--
{
Return (One)
}
}
Else
{
Store (Zero, Local0) // We're ready
}
}

Store (0x0FA0, Local0) // Timeout 200ms (50us * 4000)
While (Local0)
{
If (And (HSTS, One)) // Host Busy?
{
Decrement (Local0)
Stall (0x32) // Wait 50us
If (LEqual (Local0, Zero))
{
KILL ()
}
}
Else
{
Return (Zero) // Success
}
}

Return (One) // Failure
}

Method (COMP, 0, Serialized) // Check if last operation completed
{
Store (0x0FA0, Local0) // Timeout 200ms in 50us steps
While (Local0)
{
If (And (HSTS, 0x02)) // Completion Status?
{
Return (One) // Operation Completed
}
Else
{
Decrement (Local0)
Stall (0x32)
If (LEqual (Local0, Zero))
{
KILL ()
}
}
}

Return (Zero) // Failure
}

Method (KILL, 0, Serialized) // Kill all SMBus communication
{
Or (HCON, 0x02, HCON) // Send Kill
Or (HSTS, 0xFF, HSTS) // Clean Status
}

Device (BUS0)
{
Name (_CID, "smbus")
Name (_ADR, Zero)
Device (DVL0)
{
Name (_ADR, 0x57)
Name (_CID, "diagsvault")
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x03)
{
"address",
0x57,
Buffer (One)
{
Zero
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
}
}


That is for now..more to come after I(we?) found more info...
Clubber_77
post Nov 5 2009, 05:48 PM
Post #2
There is a question - that it will give to us, users of mobile platforms?
THe KiNG
post Nov 5 2009, 08:41 PM
Post #3
QUOTE (Clubber_77 @ Nov 5 2009, 06:48 PM) *
There is a question - that it will give to us, users of mobile platforms?

I'm not sure I understand your question "that" might be "what"?
Slice
post Nov 5 2009, 09:18 PM
Post #4
QUOTE (THe KiNG @ Nov 6 2009, 12:41 AM) *
I'm not sure I understand your question "that" might be "what"?

I think so.
He want to ask is there any sense to get SMBUS support for PC?
In macbook SMBUS is used for SmartBattery that we have no. And I don't know any device in my Dell depending on the bus.
Yes, Intel chipset contains the device to manage the bus but laptop manufactures don't use it.
i3-2120 GA-H61M-S1 UEFI, Radeon HD6670-UEFI, ALC887(VoodooHDA 2.8.7), OS⌘10.9.5, OS⌘ 10.7.5 Clover FakeSMC_plugins_v3 Realtek LAN v3.1.2
yeehaa
post Nov 5 2009, 11:21 PM
Post #5
QUOTE (Slice @ Nov 5 2009, 09:18 PM) *
I think so.
He want to ask is there any sense to get SMBUS support for PC?
In macbook SMBUS is used for SmartBattery that we have no. And I don't know any device in my Dell depending on the bus.
Yes, Intel chipset contains the device to manage the bus but laptop manufactures don't use it.


the battery and motion sensor could be moved to the EC device so that we may have vanilla battery and with some progress on fakesmc front, maybe motion sensor also in the future. it looks like there is no particular reason to load the SMBUS related kexts, but after i did that, my battery backup increased by 25-35% approximately. no idea, how!
GA-H55M-S2V, Core i3-530, Galaxy Geforce 210, Kingston 4Gb 1600DDR3, SATA HD and DVDRW, Kingston SSD System Drive
THe KiNG
post Nov 6 2009, 07:13 AM
Post #6
On desktops we have no EC but Super I/O, Mark did some great progress porting lm-sensors stuff.
On mobile most cases there is no Super I/O and all stuff is managed via SMBus/EC/ACPI.
I still think we need first to understand how this things works(for aplle) and what we can fix for us...this is not a simple job like fixing some error...
tea
post Nov 6 2009, 07:20 AM
Post #7
QUOTE
so I started to dig deep and find what does those registers and methods in our region of interest:

You forget proof link http://www.coreboot.org
THe KiNG
post Nov 6 2009, 10:05 AM
Post #8
QUOTE (tea @ Nov 6 2009, 08:20 AM) *
You forget proof link http://www.coreboot.org

I don't understand what you mean, what proof?
You mean from where I collected the info?
Yes coreboot was one of my source, something wrong with that?
tea
post Nov 6 2009, 10:10 AM
Post #9
No no, all correct. Just coreboot very interesting project and you forget post link, where you have collected the information. Sorry smile.gif
THe KiNG
post Nov 6 2009, 11:15 AM
Post #10
Indeed is a very interesting project, and it has a lot of useful info wink.gif
Most of the info came from there, but not for EC and some SMBus part.
Slice
post Nov 11 2009, 09:02 AM
Post #11
Look also here.
My Dell 1525 is very similar to MacBook4,1 (same CPU, chipset, video and so on) but
MacBook
CODE
\_SB.PCI0.LPCB.EC.SMB0
- SMBus located @ EC (PNP0C09) @ LPC
HackBook
CODE
\_SB.PCI0.LPCB.WSEC
- WSEC (PNP0C02) @LPC
and SMBus is absent in original DSDT.
I think it is because the manufacture doesn't use it in the hardware.
i3-2120 GA-H61M-S1 UEFI, Radeon HD6670-UEFI, ALC887(VoodooHDA 2.8.7), OS⌘10.9.5, OS⌘ 10.7.5 Clover FakeSMC_plugins_v3 Realtek LAN v3.1.2
THe KiNG
post Nov 11 2009, 07:04 PM
Post #12
Here on my ASUS M50SV, SMBus stuff is present(o/c is not like on apple) but there are similar stuff also with EC...:
CODE
Name (SMBS, 0x0400)
......
Scope (\)
{
OperationRegion (SMB0, SystemIO, SMBS, 0x10)
Field (SMB0, ByteAcc, NoLock, Preserve)
{
HSTS, 8,
SSTS, 8,
HSTC, 8,
HCMD, 8,
HADR, 8,
HDT0, 8,
HDT1, 8,
BLKD, 8,
SLCT, 8,
SHCM, 8,
SLEV, 16,
SLDT, 16,
SCFG, 8,
SADR, 8
}

Name (RBUF, Package (0x20) {})
Method (HBSY, 0, NotSerialized)
{
Store (0x00FFFFFF, Local0)
While (Local0)
{
And (HSTS, One, Local1)
If (LNot (Local1))
{
Return (Zero)
}

Decrement (Local0)
}

Return (One)
}
........
Scope (_SB.PCI0)
{
Device (BAT0)
{
Name (_HID, EisaId ("PNP0C0A"))
Name (_UID, Zero)
Name (_PCL, Package (0x01)
{
PCI0
})
Method (_STA, 0, NotSerialized)
{
If (^^SBRG.EC0.BATP (Zero))
{
Return (0x1F)
}
Else
{
Return (0x0F)
}
}

Still trying to put things in place and see if I can get something from SMBus working...
THe KiNG
post Nov 12 2009, 04:22 AM
Post #13
And IS POSSIBLE!



Is not 100% functional yet but is working laugh.gif
No extra battery kext just DSDT, I love this stuff...
Slice
post Nov 12 2009, 08:51 AM
Post #14
off topic
If you want "AC Charger Information" fill 6 byte in ACID key in FakeSMC.

SMBus sometimes is used in PC as access to temperature sensors. Check with Everest in Windows.
i3-2120 GA-H61M-S1 UEFI, Radeon HD6670-UEFI, ALC887(VoodooHDA 2.8.7), OS⌘10.9.5, OS⌘ 10.7.5 Clover FakeSMC_plugins_v3 Realtek LAN v3.1.2
THe KiNG
post Nov 13 2009, 07:48 PM
Post #15
Bah I've stopped playing with this crap, is not working proper, and dosen't worth the trouble(too much crap to find/fix)....better use my time for something that isn't supported/fixed yet.
I'm back to good battery kernel driver that works pretty well...

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