Project OS X Forums > Time, Timr, Tmr Device

Project OS X Forums > OS X 10.6 (Snow Leopard) > Development

Slice

Mar 22 2010, 10:24 AM

Is there anybody knows what is the device and how it used on other OSes?
It always present.
Samsung laptop with ATI chipset.

CODE

    | +-o TIME  <class IOACPIPlatformDevice, registered, matched, active, busy 0, retain count 6>
    | |   {
    | |     "IODeviceMemory" = (({"address"=0x40,"length"=0x4}))
    | |     "name" = <"PNP0100">
    | |     "IOInterruptControllers" = ("8259-pic")
    | |     "IOInterruptSpecifiers" = (<0000000000000000>)
    | |     "_STA" = 0xf
    | |   }

Dell Inspiron with Intel chipset

CODE

    | +-o TIMR  <class IOACPIPlatformDevice, id 0x100000127, registered, matched, active, busy 0 (10 ms), retain 6>
    | |   {
    | |     "name" = <504e503031303000>
    | |     "_STA" = 0xf
    | |     "IODeviceMemory" = (({"address"=0x40,"length"=0x4}),({"address"=0x50,"length"=0x4}))
    | |   }

Datasheet Click to view attachment

CODE

;The PIT is commonly located in most Intel microcomputer systems at the
;standard IO port addresses 40-43H. These standard ports could be
;different for non-standard utilization of the PIT, i.e. user defined.
;
TIMER0 equ 40h;8254 channel/counter zero(0) port address
TIMER1 equ 41h;8254 channel/counter one(1) port address

I tried to read from port 0x40 and successful. The timer is on!

It may be useful as a replacement for AppleHPET if HPET device is absent. We just need to create TMRasHPET.kext
I know precision is differ but... enough.

Superhai the Great

Mar 24 2010, 07:55 AM

It is used in all MS OS's for timing and is mandatory for all systems for that reason. Vista and Windows 7 is able to use HPET instead. For OSX to replace the HPET would be for keeping the os absolutetime absolute during c-state transitions, or maintain it on systems with variable time stamp counters during p-state transitions. The lat one is not provided by the kernel natively as it is only issue on pre-core cpus and earlier AMD cpus (the reason for why clock is running faster or slower than the real clock). I am not sure if the accuracy is enough for use during rapid transitions like c-states and p-states, and its odd frequency is also difficult.

Slice

Mar 25 2010, 08:42 AM

Thank you for the reply. It is exactly that I expected to hear.
So I think for pre-Core CPU and for chipsets without HPET chameleon, kernel and VoodooPower have to be rewritten .
I will try to do that for my Pentium M with Tiger installed.
But I am not sure that I fully understand how to use TMR instead of HPET and TSC.
The simplest way is to replace
rdtsc() to inl(0x40)
Can you correct me?

Superhai the Great

Mar 26 2010, 08:03 AM

QUOTE (Slice @ Mar 25 2010, 09:42 AM)

rdtsc() to inl(0x40)

I don't use it, but I think you have to set it up first. Also you will probably need to deal with it in some way due to it being 16 bit.

Slice

Mar 26 2010, 11:23 AM

First attempt to test. Sources, kext and utility included
Click to view attachment
Result

CODE

Timer test.
Read1 = -1073743292, Read2 = -1073743480

TSC test.
Read1 = -1811174742, Read2 = 2055
(here is a IODelay(10)
Timer test.
Read1 = -1790459257, Read2 = 1000600539

TSC test.
Read1 = 2473, Read2 = 2055

This is obviously wrong test. I want to study.

Slice

Mar 30 2010, 08:02 PM

Now I think the timer is hardwared to rdtsc...

Superhai the Great

Mar 30 2010, 08:46 PM

QUOTE (Slice @ Mar 30 2010, 10:02 PM)

Now I think the timer is hardwared to rdtsc...

No it isn't.

Slice

Dec 23 2011, 08:22 PM

This is very old 8254 timer. 16bit and slow.
Forget it!
I think we can exclude it from DSDT at all.

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