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THe KiNG
Hi,

Thanks to Galaxy who provided full dumps from his MacBookPro, ApexDE who founded the fix for J-Micron AHCI(and made me curious how he did it) and to Kabyl that always point me to the right docs, I was able to fix that IOATAFamily panic and that ugly "AppleIntelPIIXPATA: Secondary PCI IDE channel is disabled" warning on boot with a DSDT fix.

Find your Intel PATA controller in DSDT, should be on 0x001F0001, and add this code:
CODE
OperationRegion (IDET, PCI_Config, 0x40, 0x04) // IDE Timing Register
Field (IDET, WordAcc, NoLock, Preserve)
{
Offset (0x00),
M1, 8,
Offset (0x01),
M2, 8,
Offset (0x02),
M3, 8,
Offset (0x03),
M4, 8
}

Method (_DSM, 4, NotSerialized)
{
Store (0x07, M1)
Store (0xE3, M2)
Store (Zero, M3)
Store (0xC0, M4)
Return (Zero)
}


Enjoy using original kext and a clean verbose boot tongue.gif

L.E. This fix is only for Intel PATA controller!
Clubber_77
Works! Thanks! wink.gif
MacKleriker
Yep, works fine!

Thank you...

cYa
Slice
Thank you! It works.
This patch eliminates necessory in my driver
http://www.projectosx.com/forum/index.php?...ic=676&st=0
THe KiNG
Glad that I see other peopple happy with this fix(it dosen't actually enable the secondary port, you can see that Region 0 & 1 I/O ports are <unassigned>, but is a easy way to trick the driver)
Innerz
First of all, thank you so much THe KiNG for finding this DSDT trick smile.gif

I have a 965P-DS4 (ICH-8R). I don't know where to paste the provided code by THe KiNG.

CODE
Device (IDE1)
{
Name (_ADR, 0x001F0002)
OperationRegion (PCI, PCI_Config, 0x40, 0x20)
Field (PCI, DWordAcc, NoLock, Preserve)
{
ITM0, 16,
ITM1, 16,
SIT0, 4,
SIT1, 4,
Offset (0x08),
UDC0, 2,
UDC1, 2,
Offset (0x0A),
UDT0, 8,
UDT1, 8,
Offset (0x14),
ICF0, 2,
ICF1, 2,
, 6,
WPPE, 1,
, 1,
FAS0, 2,
FAS1, 2
}

Device (PRIM)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
Store (GTM (ITM0, SIT0, UDC0, UDT0, ICF0, FAS0), Local0)
Return (Local0)
}

Method (_STM, 3, NotSerialized)
{
Store (STM (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, Zero, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
CreateDWordField (Local0, 0x14, FAS)
Store (UDC, UDC0)
Store (UDT, UDT0)
Store (ICF, ICF0)
Store (FAS, FAS0)
}

Device (DRV0)
{
Name (_ADR, Zero)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF0 (ITM0, SIT0, UDC0, UDT0, ICF0, H15F, FAS0), Local0)
Return (Local0)
}
}

Device (DRV1)
{
Name (_ADR, One)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF1 (ITM0, SIT0, UDC0, UDT0, ICF0, H15F, FAS0), Local0)
Return (Local0)
}
}
}

Device (SECD)
{
Name (_ADR, One)
Method (_GTM, 0, NotSerialized)
{
Store (GTM (ITM1, SIT1, UDC1, UDT1, ICF1, FAS1), Local0)
Return (Local0)
}

Method (_STM, 3, NotSerialized)
{
Store (STM (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, Zero, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
CreateDWordField (Local0, 0x14, FAS)
Store (UDC, UDC1)
Store (UDT, UDT1)
Store (ICF, ICF1)
Store (FAS, FAS1)
}

Device (DRV0)
{
Name (_ADR, Zero)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF0 (ITM1, SIT1, UDC1, UDT1, ICF1, H15F, FAS1), Local0)
Return (Local0)
}
}

Device (DRV1)
{
Name (_ADR, One)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Store (GTF1 (ITM1, SIT1, UDC1, UDT1, ICF1, H15F, FAS1), Local0)
Return (Local0)
}
}
}
}


I'll be thankful if someone can help me.
Jingu
Okay, I manage to find the section and I added the code right after the first "}" under Device (PATA)

CODE
Device (PATA)
{
Name (_ADR, 0x001F0001)
OperationRegion (PACS, PCI_Config, 0x40, 0xC0)
Field (PACS, DWordAcc, NoLock, Preserve)
{
PRIT, 16,
Offset (0x04),
PSIT, 4,
Offset (0x08),
SYNC, 4,
Offset (0x0A),
SDT0, 2,
, 2,
SDT1, 2,
Offset (0x14),
ICR0, 4,
ICR1, 4,
ICR2, 4,
ICR3, 4,
ICR4, 4,
ICR5, 4
}

OperationRegion (IDET, PCI_Config, 0x40, 0x04)
Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 8,
M2, 8,
M3, 8,
M4, 8
}

Method (_DSM, 4, NotSerialized)
{
Store (0x07, M1)
Store (0xE3, M2)
Store (Zero, M3)
Store (0xC0, M4)
Return (Zero)
}


But after compiling dsdt.dsl into dsdt.aml

Field (IDET, WordAcc, NoLock, Preserve)
{
Offset (0x00),
M1, 8,
Offset (0x01),
M2, 8,
Offset (0x02),
M3, 8,
Offset (0x03),
M4, 8
}

keeps becoming:

Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 8,
M2, 8,
M3, 8,
M4, 8
}

BUT IT STILL WORKS! THANKS. And I don't see anymore the secondary PCI IDE channel disabled warning.

When booting up, there is however about a 10 second pause on the line: FireWire runtime power conservation disabled. (2)
THe KiNG
Was hard to find out?
I guess not tongue.gif
The offset is there that you will easy know what/where you change stuff...
Do lspci -nnvvxxx then look under IDE1(PATA) @ 40: m1 m2 m3 m4.... and you will understand.
Jingu
Yes, that was very easy to find.

I used the search function to look for occurrences of the 0x001F0001 address that you mentioned. It took me straight to the Device (PATA) section!

I understand that the offset is still there. It works fine in both 32 bit and 64 bit and that's all that matters.
Innerz
The problem is, i don't have the "0x001F0001" offset.

lspci -nnvvxxx give me this result :

CODE
04:00.0 IDE interface [0101]: JMicron Technology Corp. JMB362/JMB363 AHCI Controller [197b:2363] (rev 02) (prog-if 85 [Master SecO PriO])
Subsystem: Giga-byte Technology GA-EP45-DS5 Motherboard [1458:b000]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 17
Region 0: I/O ports at a000
Region 1: I/O ports at a400
Region 2: I/O ports at a800
Region 3: I/O ports at ac00
Region 4: I/O ports at b000
Region 5: Memory at ee100000 (32-bit, non-prefetchable)
Capabilities: [68] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] Express (v1) Legacy Endpoint, MSI 01
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Suprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100] #197b
Capabilities: [236] #68
00: 7b 19 63 23 07 00 10 00 02 85 01 01 08 00 00 00
10: 01 a0 00 00 01 a4 00 00 01 a8 00 00 01 ac 00 00
20: 01 b0 00 00 00 00 10 ee 00 00 00 00 58 14 00 b0
30: 00 00 00 00 68 00 00 00 00 00 00 00 11 01 00 00
40: b1 51 c0 00 cc 08 ff e0 20 00 00 24 00 00 00 00
50: 10 00 11 02 00 00 00 00 00 20 00 00 11 f4 03 01
60: 00 00 11 10 00 00 00 00 01 50 02 40 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 08 a0 00 a0 01 0a 00 0f aa 0f 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: c3 8b 38 00 03 45 02 00 9c 34 27 c0 49 92 00 00
d0: 18 00 80 80 01 00 00 00 00 00 eb 00 00 00 00 01
e0: 00 00 00 00 00 00 00 00 9c 34 27 c0 49 92 00 89
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Here my Click to view attachment
THe KiNG
What are you trying to do?
Do you have panic on IOATAFamily?
From what I see you have J-Micron IDE controller, do you want it as AHCI or what?
Innerz
I've an IDE DVD Drive, and JMicronATA.kext or IOATAFamily give me a kernel panic. I just want to be able to use my IDE drive. In AHCI, the IDE port seems not working at all.
THe KiNG
Sorry mate, this fix is only for Intel PATA controller, if J-MicronATA.kext dosen't work for you then you are out of luck or you need a better jmicron driver.
Innerz
Anyway, thank you for your work smile.gif
jadran
thx, tested on asrock with atom 330, works!
THe KiNG
OK seems I have to explain again for some why I did it this way.
The purpose of the comments(including the offsets) was for other to easy understand what does this modifications and why/where is the fix.
I know I can use 16 bit registers(I'm not blind and can read myself in specs) but that way people will not understand what is the fix, and apply it blindly...
Indeed INI Method is better if you don't inject other stuff in same space...

But what a hell?
For those who are so "elevate" here is the new fix:
CODE
OperationRegion (IDET, PCI_Config, 0x40, 0x04)
Field (IDET, WordAcc, NoLock, Preserve)
{
M1, 16,
M2, 16
}

Method (_INI, 0, NotSerialized)
{
Store (0xE307, M1)
Store (0xC000, M2)
}

To preserve the settings after sleep/wake add this on _WAK method:
CODE
Method (_WAK, 1, NotSerialized)
{
\_SB.PCI0.PATA._INI ()

..............................
Return (Package (0x02)
{
Zero,
Zero
})
}


@MasterChief if you have enough "balls" came here and comment my work, don't act like a chicken and comment my stuff on a forum where you know I can't reply, don't be afraid I will not ban you.
uncommah
THe KiNG,
how did you get the exact data of those registers?
THe KiNG
QUOTE (uncommah @ Nov 6 2009, 09:02 PM) *
THe KiNG,
how did you get the exact data of those registers?

Intel® ICH8 Family Datasheet page 547:
QUOTE
13.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
Note: This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.

And I said in first post, Galaxy provided me full dumps from his MacBookPro(ICH8-M)
jadran
QUOTE (THe KiNG @ Nov 6 2009, 03:56 PM) *
To preserve the settings after sleep/wake add this on _WAK method:
CODE
Method (_WAK, 1, NotSerialized)
{
\_SB.PCI0.PATA._INI ()

..............................
Return (Package (0x02)
{
Zero,
Zero
})
}


This should ba added for any board no mater what. What U think King?
I saw this in any mac dsdt.
THe KiNG
QUOTE (jadran @ Nov 7 2009, 10:17 AM) *
This should ba added for any board no mater what. What U think King?
I saw this in any mac dsdt.

I wa refering on this line:
\_SB.PCI0.PATA._INI ()
tea
I'm test your method on SATA controller (ICH7-M) on Samsung NC10 netbook. All work fine. No more KP at boot.
Thanks.
CODE
            Device (SATA)
            {
                Name (_ADR, 0x001F0002)
                OperationRegion (SACS, PCI_Config, 0x40, 0xC0)
                Field (SACS, DWordAcc, NoLock, Preserve)
                {
                    PRIT,   16,
                    SECT,   16,
                    PSIT,   4,
                    SSIT,   4,
                            Offset (0x08),
                    SYNC,   4,
                            Offset (0x0A),
                    SDT0,   2,
                        ,   2,
                    SDT1,   2,
                            Offset (0x0B),
                    SDT2,   2,
                        ,   2,
                    SDT3,   2,
                            Offset (0x14),
                    ICR0,   4,
                    ICR1,   4,
                    ICR2,   4,
                    ICR3,   4,
                    ICR4,   4,
                    ICR5,   4,
                            Offset (0x50),
                    MAPV,   2
                }

                /* Fix panic in IOATAFamily at boot time by THe KiNG
                 * http://www.projectosx.com/forum/index.php?showtopic=682&pid=3651&st=0&#entry3651
                 * ---------------------------------------
                 * #define   IDE_DECODE_ENABLE    (1 << 15)
                 * #define   IDE_SITRE        (1 << 14)
                 *
                 * #define   IDE_ISP_5_CLOCKS    (0 << 12)
                 * #define   IDE_ISP_4_CLOCKS    (1 << 12)
                 * #define   IDE_ISP_3_CLOCKS    (2 << 12)
                 *
                 * #define   IDE_RCT_4_CLOCKS    (0 <<  8)
                 * #define   IDE_RCT_3_CLOCKS    (1 <<  8)
                 * #define   IDE_RCT_2_CLOCKS    (2 <<  8)
                 * #define   IDE_RCT_1_CLOCKS    (3 <<  8)
                 *
                 * #define   IDE_DTE1        (1 <<  7)
                 * #define   IDE_PPE1        (1 <<  6)
                 * #define   IDE_IE1        (1 <<  5)
                 * #define   IDE_TIME1        (1 <<  4)
                 * #define   IDE_DTE0        (1 <<  3)
                 * #define   IDE_PPE0        (1 <<  2)
                 * #define   IDE_IE0        (1 <<  1)
                 * #define   IDE_TIME0        (1 <<  0)
                 * ---------------------------------------
                 * SATA controller in plain mode
                 *          1111 1100 0000 0000
                 *          5432 1098 7654 3210
                 * 0xE307 = 1110 0011 0000 0111 = IDE_TIME0 | IDE_IE0 | IDE_PPE0 |
                 * IDE_RCT_1_CLOCKS | IDE_ISP_3_CLOCKS | IDE_SITRE | IDE_DECODE_ENABLE
                 *
                 * 0xC000 = 1100 0000 0000 0000 = IDE_SITRE | IDE_DECODE_ENABLE
                 */

                Method (_INI, 0, NotSerialized)
                {
                    Store (0xE307, PRIT)
                    Store (0xC000, SECT)
                }
            }
THe KiNG
Even better/shorter wink.gif

BTW a very interesting article: LINK
blackCH
Thanks for this! works perfect on a HP6720s (ICH8-M) with vanilla IOATAFamily.kext. No more KPs
madmac
perhaps I just need some help with my DG41RQ.... here is the IDE0 device....
CODE
Device (IDE0)
{
Name (_ADR, 0x001F0001)
Name (^NATA, Package (0x01)
{
0x001F0001
})
Name (REGF, One)
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}

Name (TIM0, Package (0x08)
{
Package (0x04)
{
0x78,
0xB4,
0xF0,
0x0384
},

Package (0x04)
{
0x23,
0x21,
0x10,
Zero
},

Package (0x04)
{
0x0B,
0x09,
0x04,
Zero
},

Package (0x06)
{
0x78,
0x5A,
0x3C,
0x28,
0x1E,
0x14
},

Package (0x06)
{
Zero,
One,
0x02,
One,
0x02,
One
},

Package (0x06)
{
Zero,
Zero,
Zero,
One,
One,
One
},

Package (0x04)
{
0x04,
0x03,
0x02,
Zero
},

Package (0x04)
{
0x02,
One,
Zero,
Zero
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, Zero, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
OperationRegion (CFG2, PCI_Config, 0x40, 0x20)
Field (CFG2, DWordAcc, NoLock, Preserve)
{
PMPT, 4,
PSPT, 4,
PMRI, 6,
Offset (0x02),
SMPT, 4,
SSPT, 4,
SMRI, 6,
Offset (0x04),
PSRI, 4,
SSRI, 4,
Offset (0x08),
PM3E, 1,
PS3E, 1,
SM3E, 1,
SS3E, 1,
Offset (0x0A),
PMUT, 2,
, 2,
PSUT, 2,
Offset (0x0B),
SMUT, 2,
, 2,
SSUT, 2,
Offset (0x0C),
Offset (0x14),
PM6E, 1,
PS6E, 1,
SM6E, 1,
SS6E, 1,
PMCR, 1,
PSCR, 1,
SMCR, 1,
SSCR, 1,
, 4,
PMAE, 1,
PSAE, 1,
SMAE, 1,
SSAE, 1
}

Name (GMPT, Zero)
Name (GMUE, Zero)
Name (GMUT, Zero)
Name (GMCR, Zero)
Name (GSPT, Zero)
Name (GSUE, Zero)
Name (GSUT, Zero)
Name (GSCR, Zero)
Device (CHN0)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (PSCR, One, Local1)
Or (PMCR, Local1, Local0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local1)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local2)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (PMRI, Local1, PMUT, PSRI, Local2, PSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local0)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local1)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (PMRI, GMPT)
Store (Local0, GMUE)
Store (PMUT, GMUT)
Store (PMCR, GMCR)
Store (PSRI, GSPT)
Store (Local1, GSUE)
Store (PSUT, GSUT)
Store (PSCR, GSCR)
STM ()
Store (GMPT, PMRI)
Store (GMUE, Local0)
Store (GMUT, PMUT)
Store (GMCR, PMCR)
Store (GSUE, Local1)
Store (GSUT, PSUT)
Store (GSCR, PSCR)
If (And (Local0, One))
{
Store (One, PM3E)
}
Else
{
Store (Zero, PM3E)
}

If (And (Local0, 0x02))
{
Store (One, PM6E)
}
Else
{
Store (Zero, PM6E)
}

If (And (Local0, 0x04))
{
Store (One, PMAE)
}
Else
{
Store (Zero, PMAE)
}

If (And (Local1, One))
{
Store (One, PS3E)
}
Else
{
Store (Zero, PS3E)
}

If (And (Local1, 0x02))
{
Store (One, PS6E)
}
Else
{
Store (Zero, PS6E)
}

If (And (Local1, 0x04))
{
Store (One, PSAE)
}
Else
{
Store (Zero, PSAE)
}

Store (GTF (Zero, Arg1), ATA0)
Store (GTF (One, Arg2), ATA1)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA0))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA1))
}
}
}

Device (CHN1)
{
Name (_ADR, One)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (SSCR, One, Local1)
Or (SMCR, Local1, Local0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local1)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local2)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (SMRI, Local1, SMUT, SSRI, Local2, SSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local0)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local1)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (SMRI, GMPT)
Store (Local0, GMUE)
Store (SMUT, GMUT)
Store (SMCR, GMCR)
Store (SSRI, GSPT)
Store (Local1, GSUE)
Store (SSUT, GSUT)
Store (SSCR, GSCR)
STM ()
Store (GMPT, SMRI)
Store (GMUE, Local0)
Store (GMUT, SMUT)
Store (GMCR, SMCR)
Store (GSUE, Local1)
Store (GSUT, SSUT)
Store (GSCR, SSCR)
If (And (Local0, One))
{
Store (One, SM3E)
}
Else
{
Store (Zero, SM3E)
}

If (And (Local0, 0x02))
{
Store (One, SM6E)
}
Else
{
Store (Zero, SM6E)
}

If (And (Local0, 0x04))
{
Store (One, SMAE)
}
Else
{
Store (Zero, SMAE)
}

If (And (Local1, One))
{
Store (One, SS3E)
}
Else
{
Store (Zero, SS3E)
}

If (And (Local1, 0x02))
{
Store (One, SS6E)
}
Else
{
Store (Zero, SS6E)
}

If (And (Local1, 0x04))
{
Store (One, SSAE)
}
Else
{
Store (Zero, SSAE)
}

Store (GTF (Zero, Arg1), ATA2)
Store (GTF (One, Arg2), ATA3)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA2))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA3))
}
}
}

Method (GTM, 7, Serialized)
{
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x10, CHNF)
If (REGF) {}
Else
{
Return (TMD0)
}

If (And (Arg1, 0x20))
{
Or (CHNF, 0x02, CHNF)
}

Store (Match (DerefOf (Index (TIM0, One)), MEQ, Arg0, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA0)
Store (Local7, PIO0)
If (And (Arg4, 0x20))
{
Or (CHNF, 0x08, CHNF)
}

Store (Match (DerefOf (Index (TIM0, 0x02)), MEQ, Arg3, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA1)
Store (Local7, PIO1)
If (And (Arg1, 0x07))
{
Store (Arg2, Local5)
If (And (Arg1, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg1, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA0)
Or (CHNF, One, CHNF)
}

If (And (Arg4, 0x07))
{
Store (Arg5, Local5)
If (And (Arg4, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg4, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA1)
Or (CHNF, 0x04, CHNF)
}

Store (TMD0, Debug)
Return (TMD0)
}

Method (STM, 0, Serialized)
{
If (REGF)
{
Store (Zero, GMUE)
Store (Zero, GMUT)
Store (Zero, GSUE)
Store (Zero, GSUT)
If (And (CHNF, One))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA0, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GMUT)
Or (GMUE, One, GMUE)
If (LGreater (Local0, 0x02))
{
Or (GMUE, 0x02, GMUE)
}

If (LGreater (Local0, 0x04))
{
And (GMUE, 0xFD, GMUE)
Or (GMUE, 0x04, GMUE)
}
}
Else
{
If (Or (LEqual (PIO0, Ones), LEqual (PIO0, Zero)))
{
If (And (LLess (DMA0, Ones), LGreater (DMA0, Zero)))
{
Store (DMA0, PIO0)
Or (GMUE, 0x80, GMUE)
}
}
}

If (And (CHNF, 0x04))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA1, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GSUT)
Or (GSUE, One, GSUE)
If (LGreater (Local0, 0x02))
{
Or (GSUE, 0x02, GSUE)
}

If (LGreater (Local0, 0x04))
{
And (GSUE, 0xFD, GSUE)
Or (GSUE, 0x04, GSUE)
}
}
Else
{
If (Or (LEqual (PIO1, Ones), LEqual (PIO1, Zero)))
{
If (And (LLess (DMA1, Ones), LGreater (DMA1, Zero)))
{
Store (DMA1, PIO1)
Or (GSUE, 0x80, GSUE)
}
}
}

If (And (CHNF, 0x02))
{
Or (GMUE, 0x20, GMUE)
}

If (And (CHNF, 0x08))
{
Or (GSUE, 0x20, GSUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO0, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, One)), Local0)),
Local1)
Store (Local1, GMPT)
If (LLess (Local0, 0x03))
{
Or (GMUE, 0x50, GMUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO1, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0)),
Local1)
Store (Local1, GSPT)
If (LLess (Local0, 0x03))
{
Or (GSUE, 0x50, GSUE)
}
}
}

Name (AT01, Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
})
Name (AT02, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
})
Name (AT03, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
})
Name (AT04, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
})
Name (ATA0, Buffer (0x1D) {})
Name (ATA1, Buffer (0x1D) {})
Name (ATA2, Buffer (0x1D) {})
Name (ATA3, Buffer (0x1D) {})
Name (ATAB, Buffer (0x1D) {})
CreateByteField (ATAB, Zero, CMDC)
Method (GTFB, 3, Serialized)
{
Multiply (CMDC, 0x38, Local0)
Add (Local0, 0x08, Local1)
CreateField (ATAB, Local1, 0x38, CMDX)
Multiply (CMDC, 0x07, Local0)
CreateByteField (ATAB, Add (Local0, 0x02), A001)
CreateByteField (ATAB, Add (Local0, 0x06), A005)
Store (Arg0, CMDX)
Store (Arg1, A001)
Store (Arg2, A005)
Increment (CMDC)
}

Method (GTF, 2, Serialized)
{
Store (Arg1, Debug)
Store (Zero, CMDC)
Name (ID49, 0x0C00)
Name (ID59, Zero)
Name (ID53, 0x04)
Name (ID63, 0x0F00)
Name (ID88, 0x0F00)
Name (IRDY, One)
Name (PIOT, Zero)
Name (DMAT, Zero)
If (LEqual (SizeOf (Arg1), 0x0200))
{
CreateWordField (Arg1, 0x62, IW49)
Store (IW49, ID49)
CreateWordField (Arg1, 0x6A, IW53)
Store (IW53, ID53)
CreateWordField (Arg1, 0x7E, IW63)
Store (IW63, ID63)
CreateWordField (Arg1, 0x76, IW59)
Store (IW59, ID59)
CreateWordField (Arg1, 0xB0, IW88)
Store (IW88, ID88)
}

Store (0xA0, Local7)
If (Arg0)
{
Store (0xB0, Local7)
And (CHNF, 0x08, IRDY)
If (And (CHNF, 0x10))
{
Store (PIO1, PIOT)
}
Else
{
Store (PIO0, PIOT)
}

If (And (CHNF, 0x04))
{
If (And (CHNF, 0x10))
{
Store (DMA1, DMAT)
}
Else
{
Store (DMA0, DMAT)
}
}
}
Else
{
And (CHNF, 0x02, IRDY)
Store (PIO0, PIOT)
If (And (CHNF, One))
{
Store (DMA0, DMAT)
}
}

If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00
)), DMAT))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMAT, MTR,
Zero, Zero), Local1)
If (LGreater (Local1, 0x05))
{
Store (0x05, Local1)
}

GTFB (AT01, Or (0x40, Local1), Local7)
}
Else
{
If (LAnd (And (ID63, 0xFF00), PIOT))
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x03, Local0)
Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x07)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
}

If (IRDY)
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x07, Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x06)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
Else
{
If (And (ID49, 0x0400))
{
GTFB (AT01, One, Local7)
}
}

If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF)))
{
GTFB (AT03, And (ID59, 0xFF), Local7)
}

Store (ATAB, Debug)
Return (ATAB)
}

Method (RATA, 1, NotSerialized)
{
CreateByteField (Arg0, Zero, CMDN)
Multiply (CMDN, 0x38, Local0)
CreateField (Arg0, 0x08, Local0, RETB)
Store (RETB, Debug)
Return (Concatenate (RETB, FZTF))
}
}
dong
Works here too, no more KP with IOATAFamily.kext. The sleep behavior changed. It used to wake by moving mouse, now need to press the power button.
prasys
I would like to add another thing, i've been puzzling why on earth my IOATA gives me panic eventhough its fixed in DSDT. Just on a side note, if you've patched AppleP11 kext or ATAInjectorport or some sort of dummy injectors for ata , remove em as you don't need em any longer

If you do not have this entry , for instance in my Dell PC. There were no mention of IDE or SATA anywhere in DSDT. I tried searching in address , and poof its not there. So I had to declare this by myself. Here is the entire entry , so if your BIOS lacks of IDE port thingy , you should copy and paste this to the right section. This is true especially for Dell desktops and for some of their laptops

CODE
Device (IDE1) // We'll have to declare this by ourselves , argh - I hate dell
{
Name (_ADR, 0x001F0001) //Replace the address the one from your lspci , generally its this
OperationRegion (IDET, PCI_Config, 0x40, 0x04) // IDE Timing Register
Field (IDET, WordAcc, NoLock, Preserve)
{
Offset (0x00),
M1, 8,
Offset (0x01),
M2, 8,
Offset (0x02),
M3, 8,
Offset (0x03),
M4, 8
}

Method (_DSM, 4, NotSerialized)
{
Store (0x07, M1)
Store (0xE3, M2)
Store (Zero, M3)
Store (0xC0, M4)
Return (Zero)
}

OperationRegion (PCFG, PCI_Config, Zero, 0x0100)
Field (PCFG, DWordAcc, NoLock, Preserve)
{
Offset (0x40),
TPF0, 1,
TPI0, 1,
TPP0, 1,
TPD0, 1,
TPF1, 1,
TPI1, 1,
TPP1, 1,
TPD1, 1,
TPRT, 2,
, 2,
TPIS, 2,
TPTR, 1,
TPDE, 1,
TSF0, 1,
TSI0, 1,
TSP0, 1,
TSD0, 1,
TSF1, 1,
TSI1, 1,
TSP1, 1,
TSD1, 1,
TSRT, 2,
, 2,
TSIS, 2,
TSTR, 1,
TSDE, 1,
PRTS, 2,
PIOS, 2,
SRTS, 2,
SIOS, 2,
Offset (0x48),
SCP0, 1,
SCP1, 1,
SCS0, 1,
SCS1, 1,
Offset (0x4A),
PCT0, 2,
, 2,
PCT1, 2,
Offset (0x4B),
SCT0, 2,
, 2,
SCT1, 2,
Offset (0x4C),
Offset (0x54),
PCB0, 1,
PCB1, 1,
SCB0, 1,
SCB1, 1,
, 2,
PMCR, 1,
PSCR, 1,
, 4,
FPC0, 1,
FPC1, 1,
FSC0, 1,
FSC1, 1,
PSIG, 2,
SSIG, 2,
Offset (0x58)
}

Name (GTMT, Buffer (0x14)
{
/* 0000 */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* 0008 */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* 0010 */ 0x11, 0x00, 0x00, 0x00
})
CreateDWordField (GTMT, Zero, PIO0)
CreateDWordField (GTMT, 0x04, DMA0)
CreateDWordField (GTMT, 0x08, PIO1)
CreateDWordField (GTMT, 0x0C, DMA1)
CreateDWordField (GTMT, 0x10, IFLG)
Method (GTMI, 0, NotSerialized)
{
Store (Ones, PIO0)
Store (Ones, DMA0)
Store (Ones, PIO1)
Store (Ones, DMA1)
Store (0x10, IFLG)
}

Method (UDMA, 3, NotSerialized)
{
If (Arg0)
{
Return (0x14)
}

If (Arg1)
{
If (LEqual (Arg2, 0x02))
{
Return (0x1E)
}
Else
{
Return (0x2D)
}
}
Else
{
Multiply (Subtract (0x04, Arg2), 0x1E, Local0)
Return (Local0)
}
}

Method (PIOM, 2, NotSerialized)
{
Store (0x09, Local0)
Subtract (Local0, Arg0, Local0)
Subtract (Local0, Arg1, Local0)
Multiply (Local0, 0x1E, Local0)
Return (Local0)
}

Method (GTMP, 0, NotSerialized)
{
GTMI ()
If (LEqual (TPDE, Zero))
{
Return (GTMT)
}

Or (SCP0, IFLG, IFLG)
ShiftLeft (TPI0, One, Local0)
Or (Local0, IFLG, IFLG)
ShiftLeft (SCP1, 0x02, Local0)
Or (Local0, IFLG, IFLG)
ShiftLeft (TPI1, 0x03, Local0)
Or (Local0, IFLG, IFLG)
Store (PIOM (TPIS, TPRT), PIO0)
Store (PIOM (PRTS, PIOS), PIO1)
If (SCP0)
{
Store (UDMA (FPC0, PCB0, PCT0), DMA0)
}
Else
{
If (TPD0)
{
Store (PIO0, DMA0)
}
}

If (SCP1)
{
Store (UDMA (FPC1, PCB1, PCT1), DMA1)
}
Else
{
If (TPD1)
{
Store (PIO1, DMA1)
}
}

Return (GTMT)
}

Method (GTMS, 0, NotSerialized)
{
GTMI ()
If (LEqual (TSDE, Zero))
{
Return (GTMT)
}

Or (SCS0, IFLG, IFLG)
ShiftLeft (TSI0, One, Local0)
Or (Local0, IFLG, IFLG)
ShiftLeft (SCS1, 0x02, Local0)
Or (Local0, IFLG, IFLG)
ShiftLeft (TSI1, 0x03, Local0)
Or (Local0, IFLG, IFLG)
Store (PIOM (TSIS, TSRT), PIO0)
Store (PIOM (SRTS, SIOS), PIO1)
If (SCS0)
{
Store (UDMA (FSC0, SCB0, SCT0), DMA0)
}
Else
{
If (TSD0)
{
Store (PIO0, DMA0)
}
}

If (SCS1)
{
Store (UDMA (FSC1, SCB1, SCT1), DMA1)
}
Else
{
If (TSD1)
{
Store (PIO1, DMA1)
}
}

Return (GTMT)
}

Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}

Device (PRI)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
Return (GTMP ())
}

Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}

Device (SEC0)
{
Name (_ADR, One)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}

Method (_GTM, 0, NotSerialized)
{
Return (GTMS ())
}
}
}
rob3r7o
Thanks!!!!!! works perfect on ASUS M51sn (ICH8-M) with vanilla IOATAFamily.kext. No more KPs
SL 10.6.2
Neonkoala
Is this working in 10.6.3? I'm hearing mixed reports...
THe KiNG
QUOTE (Neonkoala @ Apr 7 2010, 08:23 PM) *
Is this working in 10.6.3? I'm hearing mixed reports...

Works for me.
dinobot
QUOTE (madmac @ Nov 30 2009, 10:17 AM) *
perhaps I just need some help with my DG41RQ.... here is the IDE0 device....
CODE
Device (IDE0)
{
Name (_ADR, 0x001F0001)
Name (^NATA, Package (0x01)
{
0x001F0001
})
Name (REGF, One)
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}

Name (TIM0, Package (0x08)
{
Package (0x04)
{
0x78,
0xB4,
0xF0,
0x0384
},

Package (0x04)
{
0x23,
0x21,
0x10,
Zero
},

Package (0x04)
{
0x0B,
0x09,
0x04,
Zero
},

Package (0x06)
{
0x78,
0x5A,
0x3C,
0x28,
0x1E,
0x14
},

Package (0x06)
{
Zero,
One,
0x02,
One,
0x02,
One
},

Package (0x06)
{
Zero,
Zero,
Zero,
One,
One,
One
},

Package (0x04)
{
0x04,
0x03,
0x02,
Zero
},

Package (0x04)
{
0x02,
One,
Zero,
Zero
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, Zero, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
OperationRegion (CFG2, PCI_Config, 0x40, 0x20)
Field (CFG2, DWordAcc, NoLock, Preserve)
{
PMPT, 4,
PSPT, 4,
PMRI, 6,
Offset (0x02),
SMPT, 4,
SSPT, 4,
SMRI, 6,
Offset (0x04),
PSRI, 4,
SSRI, 4,
Offset (0x08),
PM3E, 1,
PS3E, 1,
SM3E, 1,
SS3E, 1,
Offset (0x0A),
PMUT, 2,
, 2,
PSUT, 2,
Offset (0x0B),
SMUT, 2,
, 2,
SSUT, 2,
Offset (0x0C),
Offset (0x14),
PM6E, 1,
PS6E, 1,
SM6E, 1,
SS6E, 1,
PMCR, 1,
PSCR, 1,
SMCR, 1,
SSCR, 1,
, 4,
PMAE, 1,
PSAE, 1,
SMAE, 1,
SSAE, 1
}

Name (GMPT, Zero)
Name (GMUE, Zero)
Name (GMUT, Zero)
Name (GMCR, Zero)
Name (GSPT, Zero)
Name (GSUE, Zero)
Name (GSUT, Zero)
Name (GSCR, Zero)
Device (CHN0)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (PSCR, One, Local1)
Or (PMCR, Local1, Local0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local1)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local2)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (PMRI, Local1, PMUT, PSRI, Local2, PSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local0)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local1)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (PMRI, GMPT)
Store (Local0, GMUE)
Store (PMUT, GMUT)
Store (PMCR, GMCR)
Store (PSRI, GSPT)
Store (Local1, GSUE)
Store (PSUT, GSUT)
Store (PSCR, GSCR)
STM ()
Store (GMPT, PMRI)
Store (GMUE, Local0)
Store (GMUT, PMUT)
Store (GMCR, PMCR)
Store (GSUE, Local1)
Store (GSUT, PSUT)
Store (GSCR, PSCR)
If (And (Local0, One))
{
Store (One, PM3E)
}
Else
{
Store (Zero, PM3E)
}

If (And (Local0, 0x02))
{
Store (One, PM6E)
}
Else
{
Store (Zero, PM6E)
}

If (And (Local0, 0x04))
{
Store (One, PMAE)
}
Else
{
Store (Zero, PMAE)
}

If (And (Local1, One))
{
Store (One, PS3E)
}
Else
{
Store (Zero, PS3E)
}

If (And (Local1, 0x02))
{
Store (One, PS6E)
}
Else
{
Store (Zero, PS6E)
}

If (And (Local1, 0x04))
{
Store (One, PSAE)
}
Else
{
Store (Zero, PSAE)
}

Store (GTF (Zero, Arg1), ATA0)
Store (GTF (One, Arg2), ATA1)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA0))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA1))
}
}
}

Device (CHN1)
{
Name (_ADR, One)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (SSCR, One, Local1)
Or (SMCR, Local1, Local0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local1)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local2)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (SMRI, Local1, SMUT, SSRI, Local2, SSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local0)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local1)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (SMRI, GMPT)
Store (Local0, GMUE)
Store (SMUT, GMUT)
Store (SMCR, GMCR)
Store (SSRI, GSPT)
Store (Local1, GSUE)
Store (SSUT, GSUT)
Store (SSCR, GSCR)
STM ()
Store (GMPT, SMRI)
Store (GMUE, Local0)
Store (GMUT, SMUT)
Store (GMCR, SMCR)
Store (GSUE, Local1)
Store (GSUT, SSUT)
Store (GSCR, SSCR)
If (And (Local0, One))
{
Store (One, SM3E)
}
Else
{
Store (Zero, SM3E)
}

If (And (Local0, 0x02))
{
Store (One, SM6E)
}
Else
{
Store (Zero, SM6E)
}

If (And (Local0, 0x04))
{
Store (One, SMAE)
}
Else
{
Store (Zero, SMAE)
}

If (And (Local1, One))
{
Store (One, SS3E)
}
Else
{
Store (Zero, SS3E)
}

If (And (Local1, 0x02))
{
Store (One, SS6E)
}
Else
{
Store (Zero, SS6E)
}

If (And (Local1, 0x04))
{
Store (One, SSAE)
}
Else
{
Store (Zero, SSAE)
}

Store (GTF (Zero, Arg1), ATA2)
Store (GTF (One, Arg2), ATA3)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA2))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA3))
}
}
}

Method (GTM, 7, Serialized)
{
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x10, CHNF)
If (REGF) {}
Else
{
Return (TMD0)
}

If (And (Arg1, 0x20))
{
Or (CHNF, 0x02, CHNF)
}

Store (Match (DerefOf (Index (TIM0, One)), MEQ, Arg0, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA0)
Store (Local7, PIO0)
If (And (Arg4, 0x20))
{
Or (CHNF, 0x08, CHNF)
}

Store (Match (DerefOf (Index (TIM0, 0x02)), MEQ, Arg3, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA1)
Store (Local7, PIO1)
If (And (Arg1, 0x07))
{
Store (Arg2, Local5)
If (And (Arg1, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg1, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA0)
Or (CHNF, One, CHNF)
}

If (And (Arg4, 0x07))
{
Store (Arg5, Local5)
If (And (Arg4, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg4, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA1)
Or (CHNF, 0x04, CHNF)
}

Store (TMD0, Debug)
Return (TMD0)
}

Method (STM, 0, Serialized)
{
If (REGF)
{
Store (Zero, GMUE)
Store (Zero, GMUT)
Store (Zero, GSUE)
Store (Zero, GSUT)
If (And (CHNF, One))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA0, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GMUT)
Or (GMUE, One, GMUE)
If (LGreater (Local0, 0x02))
{
Or (GMUE, 0x02, GMUE)
}

If (LGreater (Local0, 0x04))
{
And (GMUE, 0xFD, GMUE)
Or (GMUE, 0x04, GMUE)
}
}
Else
{
If (Or (LEqual (PIO0, Ones), LEqual (PIO0, Zero)))
{
If (And (LLess (DMA0, Ones), LGreater (DMA0, Zero)))
{
Store (DMA0, PIO0)
Or (GMUE, 0x80, GMUE)
}
}
}

If (And (CHNF, 0x04))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA1, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GSUT)
Or (GSUE, One, GSUE)
If (LGreater (Local0, 0x02))
{
Or (GSUE, 0x02, GSUE)
}

If (LGreater (Local0, 0x04))
{
And (GSUE, 0xFD, GSUE)
Or (GSUE, 0x04, GSUE)
}
}
Else
{
If (Or (LEqual (PIO1, Ones), LEqual (PIO1, Zero)))
{
If (And (LLess (DMA1, Ones), LGreater (DMA1, Zero)))
{
Store (DMA1, PIO1)
Or (GSUE, 0x80, GSUE)
}
}
}

If (And (CHNF, 0x02))
{
Or (GMUE, 0x20, GMUE)
}

If (And (CHNF, 0x08))
{
Or (GSUE, 0x20, GSUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO0, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, One)), Local0)),
Local1)
Store (Local1, GMPT)
If (LLess (Local0, 0x03))
{
Or (GMUE, 0x50, GMUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO1, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0)),
Local1)
Store (Local1, GSPT)
If (LLess (Local0, 0x03))
{
Or (GSUE, 0x50, GSUE)
}
}
}

Name (AT01, Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
})
Name (AT02, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
})
Name (AT03, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
})
Name (AT04, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
})
Name (ATA0, Buffer (0x1D) {})
Name (ATA1, Buffer (0x1D) {})
Name (ATA2, Buffer (0x1D) {})
Name (ATA3, Buffer (0x1D) {})
Name (ATAB, Buffer (0x1D) {})
CreateByteField (ATAB, Zero, CMDC)
Method (GTFB, 3, Serialized)
{
Multiply (CMDC, 0x38, Local0)
Add (Local0, 0x08, Local1)
CreateField (ATAB, Local1, 0x38, CMDX)
Multiply (CMDC, 0x07, Local0)
CreateByteField (ATAB, Add (Local0, 0x02), A001)
CreateByteField (ATAB, Add (Local0, 0x06), A005)
Store (Arg0, CMDX)
Store (Arg1, A001)
Store (Arg2, A005)
Increment (CMDC)
}

Method (GTF, 2, Serialized)
{
Store (Arg1, Debug)
Store (Zero, CMDC)
Name (ID49, 0x0C00)
Name (ID59, Zero)
Name (ID53, 0x04)
Name (ID63, 0x0F00)
Name (ID88, 0x0F00)
Name (IRDY, One)
Name (PIOT, Zero)
Name (DMAT, Zero)
If (LEqual (SizeOf (Arg1), 0x0200))
{
CreateWordField (Arg1, 0x62, IW49)
Store (IW49, ID49)
CreateWordField (Arg1, 0x6A, IW53)
Store (IW53, ID53)
CreateWordField (Arg1, 0x7E, IW63)
Store (IW63, ID63)
CreateWordField (Arg1, 0x76, IW59)
Store (IW59, ID59)
CreateWordField (Arg1, 0xB0, IW88)
Store (IW88, ID88)
}

Store (0xA0, Local7)
If (Arg0)
{
Store (0xB0, Local7)
And (CHNF, 0x08, IRDY)
If (And (CHNF, 0x10))
{
Store (PIO1, PIOT)
}
Else
{
Store (PIO0, PIOT)
}

If (And (CHNF, 0x04))
{
If (And (CHNF, 0x10))
{
Store (DMA1, DMAT)
}
Else
{
Store (DMA0, DMAT)
}
}
}
Else
{
And (CHNF, 0x02, IRDY)
Store (PIO0, PIOT)
If (And (CHNF, One))
{
Store (DMA0, DMAT)
}
}

If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00
)), DMAT))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMAT, MTR,
Zero, Zero), Local1)
If (LGreater (Local1, 0x05))
{
Store (0x05, Local1)
}

GTFB (AT01, Or (0x40, Local1), Local7)
}
Else
{
If (LAnd (And (ID63, 0xFF00), PIOT))
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x03, Local0)
Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x07)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
}

If (IRDY)
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x07, Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x06)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
Else
{
If (And (ID49, 0x0400))
{
GTFB (AT01, One, Local7)
}
}

If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF)))
{
GTFB (AT03, And (ID59, 0xFF), Local7)
}

Store (ATAB, Debug)
Return (ATAB)
}

Method (RATA, 1, NotSerialized)
{
CreateByteField (Arg0, Zero, CMDN)
Multiply (CMDN, 0x38, Local0)
CreateField (Arg0, 0x08, Local0, RETB)
Store (RETB, Debug)
Return (Concatenate (RETB, FZTF))
}
}

Hello
Does this work on your dg41rq? I've got one with a core 2 duo and a sparkle geforce 9800 and using kext's I've found in a few different sources it works pretty well, sleep doesnt work, I mean it goes to sleep but it crashes when it wakes up. I looks ok for a second and then I get the non beach ball spinning thing. Is the the modified dsdt or one you need modified? The one I made has 3 warnings and I cant figure out if it even helps. Thanks D
CODE
Device (IDE0)
{
Name (_ADR, 0x001F0001)
Name (^NATA, Package (0x01)
{
0x001F0001
})
Name (REGF, One)
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}

Name (TIM0, Package (0x08)
{
Package (0x04)
{
0x78,
0xB4,
0xF0,
0x0384
},

Package (0x04)
{
0x23,
0x21,
0x10,
Zero
},

Package (0x04)
{
0x0B,
0x09,
0x04,
Zero
},

Package (0x06)
{
0x78,
0x5A,
0x3C,
0x28,
0x1E,
0x14
},

Package (0x06)
{
Zero,
One,
0x02,
One,
0x02,
One
},

Package (0x06)
{
Zero,
Zero,
Zero,
One,
One,
One
},

Package (0x04)
{
0x04,
0x03,
0x02,
Zero
},

Package (0x04)
{
0x02,
One,
Zero,
Zero
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, Zero, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
OperationRegion (CFG2, PCI_Config, 0x40, 0x20)
Field (CFG2, DWordAcc, NoLock, Preserve)
{
PMPT, 4,
PSPT, 4,
PMRI, 6,
Offset (0x02),
SMPT, 4,
SSPT, 4,
SMRI, 6,
Offset (0x04),
PSRI, 4,
SSRI, 4,
Offset (0x08),
PM3E, 1,
PS3E, 1,
SM3E, 1,
SS3E, 1,
Offset (0x0A),
PMUT, 2,
, 2,
PSUT, 2,
Offset (0x0B),
SMUT, 2,
, 2,
SSUT, 2,
Offset (0x0C),
Offset (0x14),
PM6E, 1,
PS6E, 1,
SM6E, 1,
SS6E, 1,
PMCR, 1,
PSCR, 1,
SMCR, 1,
SSCR, 1,
, 4,
PMAE, 1,
PSAE, 1,
SMAE, 1,
SSAE, 1
}

Name (GMPT, Zero)
Name (GMUE, Zero)
Name (GMUT, Zero)
Name (GMCR, Zero)
Name (GSPT, Zero)
Name (GSUE, Zero)
Name (GSUT, Zero)
Name (GSCR, Zero)
Device (CHN0)
{
Name (_ADR, Zero)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (PSCR, One, Local1)
Or (PMCR, Local1, Local0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local1)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local2)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (PMRI, Local1, PMUT, PSRI, Local2, PSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (PMAE, 0x02, Local3)
ShiftLeft (PM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PM3E, Local3, Local0)
ShiftLeft (PMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (PSAE, 0x02, Local3)
ShiftLeft (PS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (PS3E, Local3, Local1)
ShiftLeft (PSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (PMRI, GMPT)
Store (Local0, GMUE)
Store (PMUT, GMUT)
Store (PMCR, GMCR)
Store (PSRI, GSPT)
Store (Local1, GSUE)
Store (PSUT, GSUT)
Store (PSCR, GSCR)
STM ()
Store (GMPT, PMRI)
Store (GMUE, Local0)
Store (GMUT, PMUT)
Store (GMCR, PMCR)
Store (GSUE, Local1)
Store (GSUT, PSUT)
Store (GSCR, PSCR)
If (And (Local0, One))
{
Store (One, PM3E)
}
Else
{
Store (Zero, PM3E)
}

If (And (Local0, 0x02))
{
Store (One, PM6E)
}
Else
{
Store (Zero, PM6E)
}

If (And (Local0, 0x04))
{
Store (One, PMAE)
}
Else
{
Store (Zero, PMAE)
}

If (And (Local1, One))
{
Store (One, PS3E)
}
Else
{
Store (Zero, PS3E)
}

If (And (Local1, 0x02))
{
Store (One, PS6E)
}
Else
{
Store (Zero, PS6E)
}

If (And (Local1, 0x04))
{
Store (One, PSAE)
}
Else
{
Store (Zero, PSAE)
}

Store (GTF (Zero, Arg1), ATA0)
Store (GTF (One, Arg2), ATA1)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA0))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA1))
}
}
}

Device (CHN1)
{
Name (_ADR, One)
Method (_GTM, 0, NotSerialized)
{
ShiftLeft (SSCR, One, Local1)
Or (SMCR, Local1, Local0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local1)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local1, Local3, Local1)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local2)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local2, Local3, Local2)
Return (GTM (SMRI, Local1, SMUT, SSRI, Local2, SSUT, Local0))
}

Method (_STM, 3, NotSerialized)
{
Store (Arg0, Debug)
Store (Arg0, TMD0)
ShiftLeft (SMAE, 0x02, Local3)
ShiftLeft (SM6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SM3E, Local3, Local0)
ShiftLeft (SMPT, 0x04, Local3)
Or (Local0, Local3, Local0)
ShiftLeft (SSAE, 0x02, Local3)
ShiftLeft (SS6E, One, Local4)
Or (Local3, Local4, Local3)
Or (SS3E, Local3, Local1)
ShiftLeft (SSPT, 0x04, Local3)
Or (Local1, Local3, Local1)
Store (SMRI, GMPT)
Store (Local0, GMUE)
Store (SMUT, GMUT)
Store (SMCR, GMCR)
Store (SSRI, GSPT)
Store (Local1, GSUE)
Store (SSUT, GSUT)
Store (SSCR, GSCR)
STM ()
Store (GMPT, SMRI)
Store (GMUE, Local0)
Store (GMUT, SMUT)
Store (GMCR, SMCR)
Store (GSUE, Local1)
Store (GSUT, SSUT)
Store (GSCR, SSCR)
If (And (Local0, One))
{
Store (One, SM3E)
}
Else
{
Store (Zero, SM3E)
}

If (And (Local0, 0x02))
{
Store (One, SM6E)
}
Else
{
Store (Zero, SM6E)
}

If (And (Local0, 0x04))
{
Store (One, SMAE)
}
Else
{
Store (Zero, SMAE)
}

If (And (Local1, One))
{
Store (One, SS3E)
}
Else
{
Store (Zero, SS3E)
}

If (And (Local1, 0x02))
{
Store (One, SS6E)
}
Else
{
Store (Zero, SS6E)
}

If (And (Local1, 0x04))
{
Store (One, SSAE)
}
Else
{
Store (Zero, SSAE)
}

Store (GTF (Zero, Arg1), ATA2)
Store (GTF (One, Arg2), ATA3)
}

Device (DRV0)
{
Name (_ADR, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA2))
}
}

Device (DRV1)
{
Name (_ADR, One)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA3))
}
}
}

Method (GTM, 7, Serialized)
{
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x10, CHNF)
If (REGF) {}
Else
{
Return (TMD0)
}

If (And (Arg1, 0x20))
{
Or (CHNF, 0x02, CHNF)
}

Store (Match (DerefOf (Index (TIM0, One)), MEQ, Arg0, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA0)
Store (Local7, PIO0)
If (And (Arg4, 0x20))
{
Or (CHNF, 0x08, CHNF)
}

Store (Match (DerefOf (Index (TIM0, 0x02)), MEQ, Arg3, MTR,
Zero, Zero), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0, Zero)), Local6)),
Local7)
Store (Local7, DMA1)
Store (Local7, PIO1)
If (And (Arg1, 0x07))
{
Store (Arg2, Local5)
If (And (Arg1, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg1, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA0)
Or (CHNF, One, CHNF)
}

If (And (Arg4, 0x07))
{
Store (Arg5, Local5)
If (And (Arg4, 0x02))
{
Add (Local5, 0x02, Local5)
}

If (And (Arg4, 0x04))
{
Add (Local5, 0x04, Local5)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local5)),
DMA1)
Or (CHNF, 0x04, CHNF)
}

Store (TMD0, Debug)
Return (TMD0)
}

Method (STM, 0, Serialized)
{
If (REGF)
{
Store (Zero, GMUE)
Store (Zero, GMUT)
Store (Zero, GSUE)
Store (Zero, GSUT)
If (And (CHNF, One))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA0, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GMUT)
Or (GMUE, One, GMUE)
If (LGreater (Local0, 0x02))
{
Or (GMUE, 0x02, GMUE)
}

If (LGreater (Local0, 0x04))
{
And (GMUE, 0xFD, GMUE)
Or (GMUE, 0x04, GMUE)
}
}
Else
{
If (Or (LEqual (PIO0, Ones), LEqual (PIO0, Zero)))
{
If (And (LLess (DMA0, Ones), LGreater (DMA0, Zero)))
{
Store (DMA0, PIO0)
Or (GMUE, 0x80, GMUE)
}
}
}

If (And (CHNF, 0x04))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMA1, MTR,
Zero, Zero), Local0)
If (LGreater (Local0, 0x05))
{
Store (0x05, Local0)
}

Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
GSUT)
Or (GSUE, One, GSUE)
If (LGreater (Local0, 0x02))
{
Or (GSUE, 0x02, GSUE)
}

If (LGreater (Local0, 0x04))
{
And (GSUE, 0xFD, GSUE)
Or (GSUE, 0x04, GSUE)
}
}
Else
{
If (Or (LEqual (PIO1, Ones), LEqual (PIO1, Zero)))
{
If (And (LLess (DMA1, Ones), LGreater (DMA1, Zero)))
{
Store (DMA1, PIO1)
Or (GSUE, 0x80, GSUE)
}
}
}

If (And (CHNF, 0x02))
{
Or (GMUE, 0x20, GMUE)
}

If (And (CHNF, 0x08))
{
Or (GSUE, 0x20, GSUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO0, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, One)), Local0)),
Local1)
Store (Local1, GMPT)
If (LLess (Local0, 0x03))
{
Or (GMUE, 0x50, GMUE)
}

And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIO1, MTR,
Zero, Zero), 0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0)),
Local1)
Store (Local1, GSPT)
If (LLess (Local0, 0x03))
{
Or (GSUE, 0x50, GSUE)
}
}
}

Name (AT01, Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
})
Name (AT02, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
})
Name (AT03, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
})
Name (AT04, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
})
Name (ATA0, Buffer (0x1D) {})
Name (ATA1, Buffer (0x1D) {})
Name (ATA2, Buffer (0x1D) {})
Name (ATA3, Buffer (0x1D) {})
Name (ATAB, Buffer (0x1D) {})
CreateByteField (ATAB, Zero, CMDC)
Method (GTFB, 3, Serialized)
{
Multiply (CMDC, 0x38, Local0)
Add (Local0, 0x08, Local1)
CreateField (ATAB, Local1, 0x38, CMDX)
Multiply (CMDC, 0x07, Local0)
CreateByteField (ATAB, Add (Local0, 0x02), A001)
CreateByteField (ATAB, Add (Local0, 0x06), A005)
Store (Arg0, CMDX)
Store (Arg1, A001)
Store (Arg2, A005)
Increment (CMDC)
}

Method (GTF, 2, Serialized)
{
Store (Arg1, Debug)
Store (Zero, CMDC)
Name (ID49, 0x0C00)
Name (ID59, Zero)
Name (ID53, 0x04)
Name (ID63, 0x0F00)
Name (ID88, 0x0F00)
Name (IRDY, One)
Name (PIOT, Zero)
Name (DMAT, Zero)
If (LEqual (SizeOf (Arg1), 0x0200))
{
CreateWordField (Arg1, 0x62, IW49)
Store (IW49, ID49)
CreateWordField (Arg1, 0x6A, IW53)
Store (IW53, ID53)
CreateWordField (Arg1, 0x7E, IW63)
Store (IW63, ID63)
CreateWordField (Arg1, 0x76, IW59)
Store (IW59, ID59)
CreateWordField (Arg1, 0xB0, IW88)
Store (IW88, ID88)
}

Store (0xA0, Local7)
If (Arg0)
{
Store (0xB0, Local7)
And (CHNF, 0x08, IRDY)
If (And (CHNF, 0x10))
{
Store (PIO1, PIOT)
}
Else
{
Store (PIO0, PIOT)
}

If (And (CHNF, 0x04))
{
If (And (CHNF, 0x10))
{
Store (DMA1, DMAT)
}
Else
{
Store (DMA0, DMAT)
}
}
}
Else
{
And (CHNF, 0x02, IRDY)
Store (PIO0, PIOT)
If (And (CHNF, One))
{
Store (DMA0, DMAT)
}
}

If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00
)), DMAT))
{
Store (Match (DerefOf (Index (TIM0, 0x03)), MLE, DMAT, MTR,
Zero, Zero), Local1)
If (LGreater (Local1, 0x05))
{
Store (0x05, Local1)
}

GTFB (AT01, Or (0x40, Local1), Local7)
}
Else
{
If (LAnd (And (ID63, 0xFF00), PIOT))
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x03, Local0)
Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x07)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
}

If (IRDY)
{
And (Match (DerefOf (Index (TIM0, Zero)), MGE, PIOT, MTR,
Zero, Zero), 0x07, Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x06)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
Else
{
If (And (ID49, 0x0400))
{
GTFB (AT01, One, Local7)
}
}

If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF)))
{
GTFB (AT03, And (ID59, 0xFF), Local7)
}

Store (ATAB, Debug)
Return (ATAB)
}

Method (RATA, 1, NotSerialized)
{
CreateByteField (Arg0, Zero, CMDN)
Multiply (CMDN, 0x38, Local0)
CreateField (Arg0, 0x08, Local0, RETB)
Store (RETB, Debug)
Return (Concatenate (RETB, FZTF))
}
}
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