To apply on other ICHx check the ICHx specs b/c some functions/registers may vary(e.g. ICH7 has only 4 UHCI ports and one EHCI).
The board used in this example is a mITX Intel ATOM board, that has only 1 PCI port.
You may use this guide on mATX or netbooks/notebooks.
I do not recommend using this stuff on full ATX boards, unless you know what you are doing...
So what is the benefit of this?
If you look on Apple ioregs(macmini/iMac or mobile) you will see almost on all root ports that are unused(they are not populated or dosen't get populated on card insertion) are disabled by default in EFI.
On our PC's are not, or worst on some crap BIOS some are not enabled(the right one..)
So what are the benefits other then cosmetic?
Each root port if is not disablet get IRQ's assigned, IRQ's are shared and in some cases conflicts may happen, not to mention that on our BIOS'es PCI IRQ routing table is pure crap on most cases, so to prevent an IRQ storm, here is how you can disable/enable them:
The registers part, see page 299, 7.1.56 FD—Function Disable Register, ICH7 IO Controller HUB:
CODE
OperationRegion (FDIS, SystemMemory, 0xFED1C000, 0x4000)
Field (FDIS, DWordAcc, Lock, Preserve)
{
Offset(0x3418), // Function Disable
, 1, // Offset: 3418h, Reserved
PATD, 1, // Offset: 3418h, Bit: 1 Parallel ATA Disable
SATD, 1, // Offset: 3418h, Bit: 2 Serial ATA Disable
SMBD, 1, // Offset: 3418h, Bit: 3 SM Bus Disable
HDAD, 1, // Offset: 3418h, Bit: 4 Intel High Definition Audio Disable
A97D, 1, // Offset: 3418h, Bit: 5 AC ‘97 Audio Disable
M97D, 1, // Offset: 3418h, Bit: 6 AC ‘97 Modem Disable
ILND, 1, // Offset: 3418h, Bit: 7 Internal LAN Disable
US1D, 1, // Offset: 3419h, UHCI #1 Disable
US2D, 1, // Offset: 3419h, Bit: 1 UHCI #2 Disable
US3D, 1, // Offset: 3419h, Bit: 2 UHCI #3 Disable
US4D, 1, // Offset: 3419h, Bit: 3 UHCI #4 Disable
, 2, // Offset: 3419h, Bit: 4&5 Reserved
LPBD, 1, // Offset: 3419h, Bit: 6 LPC Bridge Disable
EHCD, 1, // Offset: 3419h, Bit: 7 EHCI Disable
Offset(0x341A), // Function Disable Root Ports
RP1D, 1, // Offset: 341Ah, Root Port 1 Disable
RP2D, 1, // Offset: 341Ah, Bit: 1 Root Port 2 Disable
RP3D, 1, // Offset: 341Ah, Bit: 2 Root Port 3 Disable
RP4D, 1, // Offset: 341Ah, Bit: 3 Root Port 4 Disable
RP5D, 1, // Offset: 341Ah, Bit: 4 Root Port 5 Disable
RP6D, 1, // Offset: 341Ah, Bit: 5 Root Port 6 Disable
}
Field (FDIS, DWordAcc, Lock, Preserve)
{
Offset(0x3418), // Function Disable
, 1, // Offset: 3418h, Reserved
PATD, 1, // Offset: 3418h, Bit: 1 Parallel ATA Disable
SATD, 1, // Offset: 3418h, Bit: 2 Serial ATA Disable
SMBD, 1, // Offset: 3418h, Bit: 3 SM Bus Disable
HDAD, 1, // Offset: 3418h, Bit: 4 Intel High Definition Audio Disable
A97D, 1, // Offset: 3418h, Bit: 5 AC ‘97 Audio Disable
M97D, 1, // Offset: 3418h, Bit: 6 AC ‘97 Modem Disable
ILND, 1, // Offset: 3418h, Bit: 7 Internal LAN Disable
US1D, 1, // Offset: 3419h, UHCI #1 Disable
US2D, 1, // Offset: 3419h, Bit: 1 UHCI #2 Disable
US3D, 1, // Offset: 3419h, Bit: 2 UHCI #3 Disable
US4D, 1, // Offset: 3419h, Bit: 3 UHCI #4 Disable
, 2, // Offset: 3419h, Bit: 4&5 Reserved
LPBD, 1, // Offset: 3419h, Bit: 6 LPC Bridge Disable
EHCD, 1, // Offset: 3419h, Bit: 7 EHCI Disable
Offset(0x341A), // Function Disable Root Ports
RP1D, 1, // Offset: 341Ah, Root Port 1 Disable
RP2D, 1, // Offset: 341Ah, Bit: 1 Root Port 2 Disable
RP3D, 1, // Offset: 341Ah, Bit: 2 Root Port 3 Disable
RP4D, 1, // Offset: 341Ah, Bit: 3 Root Port 4 Disable
RP5D, 1, // Offset: 341Ah, Bit: 4 Root Port 5 Disable
RP6D, 1, // Offset: 341Ah, Bit: 5 Root Port 6 Disable
}
Now you can easy see what can be disabled/enabled, keep in mind that default value for enable is 0 and for disable is 1.
On my Atom board only first 2 root ports are used 0x001E0000(Also know in Apple DSDT as PCIB) for the PCI slot and 0x001C0000 for internal LAN, root port 3 and 4 are eating resources for nothing, 5 and 6 are disabled by Intel in EFI.
So lets disable RP03 and RP04:
Create a new Method right before _WAK one:
CODE
Method (PINI, 0, NotSerialized) // For PCI0/Wake INI
{
Store (One, RP3D)
Store (One, RP4D)
}
{
Store (One, RP3D)
Store (One, RP4D)
}
To make sure it will stay disabled after wake, we have to add a call for it on _WAK method:
CODE
Method (_WAK, 1, NotSerialized)
{
PINI ()
// ....... // Rest of your stuff from _WAK method
}
{
PINI ()
// ....... // Rest of your stuff from _WAK method
}
And finally call it on PCI0 _INI:
CODE
Device (PCI0)
{
Method (_INI, 0, NotSerialized)
{
PINI ()
}
// ....... //
}
{
Method (_INI, 0, NotSerialized)
{
PINI ()
}
// ....... //
}
That's it.
Enjoy!


